L6710 STMicroelectronics, L6710 Datasheet
L6710
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L6710 Summary of contents
Page 1
... Current mode until UVP N. HGATE2 35 21 PHASE2 LGATE2 38 18 PGND 39 17 LGATE1 16 40 VCCDR 41 15 PHASE1 14 42 HGATE1 L6710 TQFP44 ( 1mm) Exposed Pad L6710TR (Tape & Reel) OSC / FAULT ISEN2 PGNDS ISEN1 FBG FBR N.C. N.C. OUTEN VSEN REF_OUT 1/34 ...
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... L6710 BLOCK DIAGRAM OSC / FAULT OSC / FAULT OUTEN OUTEN PGOOD PGOOD DIGITAL DIGITAL SOFT-START SOFT-START VID5 VID5 VID4 VID4 DAC DAC VID3 VID3 VID2 VID2 VID1 VID1 VID0 VID0 CH1 OCP CH1 OCP VSEN VSEN 32k 32k 32k 32k I I FBG ...
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... The net connecting the pin to the sense point must be routed as close as possible to the PGNDS net in order to couple in common mode any picked-up noise. Description This pin has to be connected to the low-side mosfet drain dsON. This pin has to be connected to the low-side mosfet drain dsON. L6710 3/34 ...
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... L6710 PIN FUNCTION (continued) N Name 22 OSC/FAULT Oscillator pin. It allows programming the switching frequency of each channel: the equivalent switching frequency at the load side results in being doubled. Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin with an internal gain of 6kHz/µA (See relevant section for details). If the pin is not connected, the switching frequency is 150kHz for each channel (300kHz on the load) ...
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... OSC = OPEN; Tj=0°C to 125°C OSC = OPEN OSC = OPEN; I =70µA FB OVP or UVP Active VID0 to VID5 see Table1; FBR = V ; FBG = GND OUT VID0 to VID5 see Table1; VIDx = GND VIDx = OPEN Input Low Input High COMP=10pF L6710 Min Typ Max Unit 7 0.5 1 1.5 mA 8.2 9 ...
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... L6710 ELECTRICAL CHARACTERISTICS (continued 12V±15 70°C unless otherwise specified Symbol Parameter DIFFERENTIAL AMPLIFIER (REMOTE BUFFER) DC Gain CMRR Common Mode Rejection Ratio SR Slew Rate DIFFERENTIAL CURRENT SENSING I , Bias Current ISEN1 I ISEN2 I Bias Current PGNDSx I , Bias Current at ISEN1 Over Current Threshold I ISEN2 ...
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... VID3 VID2 VID1 VID0 L6710 Output Voltage (V) (*) 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 7/34 ...
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... ON the lower driver and driving high the FAULT pin. 8/34 VCCDR VCC 41 5 BOOT1 BOOT2 3 31 HGATE1 HGATE2 43 35 PHASE1 PHASE2 42 36 LGATE1 LGATE2 40 38 ISEN1 ISEN2 L6710 PGNDS To PGNDS 20 Rg PGND 39 VID5 29 VID4 28 PGOOD 30 VID3 27 VSEN 13 VID2 26 VID1 25 VID0 REF_OUT 12 22 ...
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... S µ 800 700 600 500 400 300 200 100 0 100 125 150 150 ) connected between OSC pin and OSC 6 ⋅ 7.422 10 + ----------------------------- ( ) R KΩ ⋅ 6.457 10 = 150kHz + ----------------------------- ( ) R KΩ 250 350 450 550 Frequency (KHz) L6710 650 volt- PROG 9/34 ...
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... L6710 The voltage identification (VID*) pin configuration also sets the power-good thresholds (PGOOD) and the Over / Under Voltage protection (OVP/UVP) thresholds. The reference used for the regulation is also available externally on the pin REF_OUT; this pin must be filtered vs. SGND with 47nF (typ.) ceramic capacitor to allow compatibility with VRD10.0 that is to allow dynamic VID transitions that causes reference variations of 12.5mV / 5 µ ...
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... CH3 = LGATE1; CH4 = LGATE2 ) and internally converted into a current. The transconductance ratio is ⋅ SENSE PHAS Ex 50µA 50µ ----------------------------------------------- - = the low side mosfet and Rg is the transcon- dsON ⋅ SENSE PHAS ----------------------------------------------- - INFO L6710 I + INFO x is the current PHASEx dsON 11/34 ...
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... L6710 Since the current is read in differential mode, also negative current information is kept; this allow the de- vice to check for dangerous returning current between the two phases assuring the complete equalization between the phase's currents. From the current information of each phase, information about the total cur- ...
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... The high side mosfets can be turned INFOx V – Vout ⋅ ------------------------------------ - Ton + = OCPx L Resulting Output IN characteristic Desired Output characteristic and UVP threshold IN I =2·I OCP OCPx =70 µ Limited Output Voltage ON OCPx V – Vout ⋅ ⋅ ------------------------------------- - 0. L6710 OCPx lim- ON limited ON I OUT (I INFOx 13/34 ...
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... L6710 output voltage reaches the under-voltage threshold (V are turned off, the FAULT pin is driven high and the device stops working. Cycle the power supply to re- start operation. The maximum average current during the Constant-Current behavior results X,TOT In this particular situation, the switching frequency results reduced. The ON time is the maximum allowed ...
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... Total Current Info (I Total Current Info (I Ref Ref ) is sourced from I NFOx NSE ⋅ ⋅ --------------------- - OAD Rg is its equivalent output resistance and 70µA at the OC in- INFO1 INFO2 ⋅ 70 µ – INTERV ENTION – FB ESR DROP ( OUT OUT + INFO1 INFO1 INFO2 INFO2 L6710 V DROOP 15/34 ...
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... L6710 is used for a VRM module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise ...
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... Forcing the OUTEN pin to a voltage lower than 0.4V (Typ.) disables the device: all the power mos- fets and protections are turned off until the condition is removed. Figure 10. Soft Start CCDR V LGATEx V OUT PGOOD 2048 Clock Cycles Timing Diagram OUTEN Turn ON threshold LGATEx OSC/FAULT OUTEN REF_OUT Acquisition: CH1=PGOOD; CH2=REF_OUT; CH3=VOUT; CH4=LGATEx) L6710 17/34 ...
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... L6710 Figure 11. Power Down: 0A (left), resistive load (right); CH1= Vout; CH2,CH3 = LS; CH4 =V in When shutting the system down, the device continues regulating until Vcc becomes lower than the turn- off threshold. After that point, the device will shut down all power mosfets. ...
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... ESR OUT OUT 2 ∆ I ⋅ L OUT ∆ ------------------------------------------------------------------------------ - OUT ⋅ ⋅ ( ⋅ OUT between 20% and 30% of the maximum output current. The inductance L V – OUT OUT ⋅ ----------------------------- - -------------- ∆ I ⋅ the input voltage and – V OUT is the output voltage. OUT L6710 19/34 ...
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... L6710 t app lic atio n The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available. MAIN CONTROL LOOP The control loop is composed by the Current Sharing control loop and the Average Current Mode control loop ...
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... D02IN1393 ⋅ ⋅ ( PWM DROOP ( – ------------------------------------------------------------------------------------------------------------------- - ⋅ -------------- - ⋅ ⋅ ------------------ - ----------------------------------- - = – ∆ OSC DROOP ⋅ ⋅ -------------- - ------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- - ⋅ ⋅ ------ - INFO2 I INFO1 OUT /2). MAX ⋅ ----------- - ⋅ ------- - + -------------- - ⋅ ⋅ //Ro + ESR DROOP ⋅ ⋅ ⋅ ------ - + s --------------- + ⋅ L6710 + 1 21/34 ...
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... L6710 Considering now that in the application of interest it can be assumed that Ro>>R R <<Ro, it results: DROOP ⋅ – LOOP 5 The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the 0dB axes with a constant -20dB/dec slope with the desired crossover frequency ω ...
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... LS mosfets Source pin. GATEx and PHASEx connections (and also PGND when no power ground plane is implemented) must also be designed to handle current peaks in excess of 2A (30 mils wide is suggested). BOOTx C BOOTx PHASEx +V C OUT VCC LOAD SGND b. PCB small signal components placement OUT LS D LOAD VCC L6710 23/34 ...
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... L6710 Figure 17. Device orientation (left) and sense nets routing (right Mosfets (30 mils wide Mosfet (30 mils wide) Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the sys- tem efficiency. The placement of other components is also important: · The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to mini- mize the loop that is created. · ...
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... Figure 18. PCB layout connections for sense nets. VIA to GND Plane EMBEDDING L6710-BASED VRMs… When embedding the VRM into the application, additional care must be taken since the whole VRM is a switching DC/DC regulator and the most common system in which it has to work is a digital system such similar ...
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... L6710 Since the generated noise is mainly due to the switching activity of the VRM, noise emissions depend on how fast the current switch. To reduce noise emission levels also possible, in addition to the previous guidelines, to reduce the current slope and then to increase the switching times: this will cause con- sequence of the higher switching time, an increase in switching losses that must be considered in the ther- mal design of the system ...
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... D1 Q1a OUTEN To R21 R2 Vcc pin L6710 EVALUATION BOARD REV.1 Figure 21. Power supply configuration Vin JP6 GNDin Vcc GNDcc Two main configurations can be distinguished: Single Supply (V (V =12V V =5V or different – Single Supply: In this case JP6 has to be completely shorted. The device is supplied with the same rail that is used for the conversion ...
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... L6710 Figure 22. Jumpers configuration: Double Supply Vin = 5V DZ1 GNDin JP6 JP2 JP1 Vcc = 12V GNDcc (a) V =12V BOOTx CCDR Figure 23. Jumpers configuration: Single Supply Vin = 12V DZ1 6.8V JP6 GNDin JP2 JP1 Vcc = Open GNDcc ( =12V CCDR Figure 24. PCB and Components Layouts ...
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... R F Output Voltage Offset Comp. Network VCC Filter Gate Resistors VCCDR Filter External divider External divider Thermal compensation Panasonic ERTJIVT102H L6710 Solder Side Vendor size SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 ...
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... Not mounted D1, D2 STPS340U D3, D4 1N4148 Inductors L1, L2 0.7 µ Mosfets Q1, Q1a, Q3, Q3a STB90NF03L Q2, Q4 STB90NF03L Devices U1 L6710 30/34 (VRD 10) (continued) OUT Description Comp Network C F Bootstrap capacitors Input ceramic capacitors VCC Filter VCCDR Filter Input Filter TDK C4532X7R1C226MT Panas. ECJ4YB1C226M ...
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... STATIC PERFORMANCES Figure 26. - System Efficiency and Mosfet Temperature (Tamb=27deg, 4CFM, 400kHz effective switching frequency Output Current [A] Figure 27. Load Regulation. 1.335 1.320 1.305 1.290 1.275 1.260 1.245 1.230 1.215 1.200 125 110 Output Current [ Q1A LS Q3A Output Current [ L6710 80 31/34 ...
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... L6710 DYNAMIC PERFORMANCES Figure 28 78A Load Transient Response. 1.325V Figure 29. Dynamic VID at 0A 0.950 V Figure 30. Dynamic VID at 78A. 0.950V 32/34 1.325V 1.325V 1.325V 1.325V 1.325V 0.950 V 0.950V ...
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... TYP. MAX. MECHANICAL DATA 0.047 0.006 0.039 0.041 0.015 0.018 0.008 0.472 0.480 0.394 0.401 0.238 0.315 0.472 0.480 0.394 0.401 0.238 0.315 Body 1.0mm 0.031 0.024 0.030 0.039 TQFP44 - EXPOSED PAD 0.003 L6710 OUTLINE AND 7278837 B (L6710) 33/34 ...
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... L6710 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...