MT8VDDT6464HG-335D1 Micron Technology Inc, MT8VDDT6464HG-335D1 Datasheet
MT8VDDT6464HG-335D1
Specifications of MT8VDDT6464HG-335D1
Related parts for MT8VDDT6464HG-335D1
MT8VDDT6464HG-335D1 Summary of contents
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... PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB, 256MB, 512MB (x64, SR) MT8VDDT1664H – 128MB MT8VDDT3264H – 256MB MT8VDDT6464H – 512MB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 200-Pin SODIMM (MO-224) 1.25in. (31.75mm) OPTIONS • Package 200-pin SODIMM (standard) 200-pin SODIMM (lead-free) • ...
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... MT8VDDT6464HG-262__ MT8VDDT6464HY-262__ 512MB MT8VDDT6464HG-26A__ 512MB MT8VDDT6464HY-26A__ 512MB 512MB MT8VDDT6464HG-265__ MT8VDDT6464HY-265__ 512MB NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT3264HG-265A1. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN ...
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Table 3: Pin Assignment (200-Pin SODIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 101 REF DQ19 103 SS 5 DQ0 55 DQ24 105 7 DQ1 57 V 107 DD 9 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS 118, 119, 120 WE#, CAS#, RAS# 35, 37, 158, 160 CK0, CK0#, CK1, CK1#, 96 121 ...
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... SS V Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU — Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. NC — No Connect: These pins should be left unconnected. 5 200-PIN DDR SODIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... SDA SA0 SA1 SA2 Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB); MT46V32M8TG (256MB); MT46V64M8TG (512MB) Lead-free modules use the following DDR SDRAM devices: MT46V16M8P (128MB); MT46V32M8P (256MB); MT46V64M8P (512MB) 6 200-PIN DDR SODIMM DQS1 DM1 DM CS# DQS DQ8 DQ DQ9 DQ ...
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... DDR SDRAM modules use internally configured quad-bank DDR SDRAMs. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-pre-fetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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Burst Length Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being program- mable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that ...
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Table 6: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES LENGTH ADDRESS WITHIN A BURST TYPE = SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1-2 ...
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... DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Figure 6: Extended Mode Register Definition Diagram 128MB Module BA1 BA0 A11 A10 Operating Mode 256MB, 512MB Modules BA1 BA0 A12 A11 A10 Operating Mode 2 E11 E10 E9 E8 ...
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Commands Figure 8, Commands Truth Table, and Figure 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 128MB DD DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 47; notes appear on pages 18–21; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 13: I Specifications and Conditions – 256MB DD DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 47; notes appear on pages 18–21; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 14: I Specifications and Conditions – 512MB DD DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 47; notes appear on pages 18–21; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 15: Capacitance Note: 11; notes appearon pages 18–21 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 16: Electrical Characteristics and Recommended AC Operating Conditions DDR SDRAM Components only Notes: ...
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Table 16: Electrical Characteristics and Recommended AC Operating Conditions (Continued) DDR SDRAM Components only AC CHARACTERISTICS PARAMETER DQ-DQS hold, DQS to first non- valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 ...
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HP min is the lesser of CL minimum and minimum actually applied to the device CK and CK/ inputs, collectively during device bank active. 31. READs and WRITEs with auto precharge are not t allowed to be ...
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The current Micron part operates below the slow- est JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 41. Random addressing changing and 50 percent of data changing at every transfer. 42. Random ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure ...
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Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read Byte ...
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Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 21: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear following matrix BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 ...
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... The value of RP, RCD, and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 128MB, 256MB, 512MB (x64, SR) ENTRY (VERSION) MT8VDDT1664H MT8VDDT3264H MT8VDDT6464H ...
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Figure 15: 200-Pin DDR SODIMM Dimensions 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (0.99) TYP U8 PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation Released (No Mark): This ...