MT8VDDT6464HG-335D1 Micron Technology Inc, MT8VDDT6464HG-335D1 Datasheet - Page 21

• Manufacturer Part Number: MT8VDDT6464HG-335D1
• Description: MODULE DDR SDRAM 512MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464HG-335D1

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 167MHz
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.4A
• Number Of Elements: 8
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1127

pdf: 09005aef8092973f, source: 09005aef80921669
DD8C16_32_64x64HG.fm - Rev. B 9/04 EN
40. The current Micron part operates below the slow-
41. Random addressing changing and 50 percent of
42. Random addressing changing and 100 percent of
43. CKE must be active (high) during the entire time a
44. I
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
similar to I
REF later.
DD
2N specifies the DQ, DQS, and DM to be
DD
2
F
except I
DD
2
Q
specifies the
DD
2
Q
is
21
45. Whenever the operating frequency is altered, not
46. Leakage number reflects the worst case leakage
47. When an input signal is HIGH or LOW, it is
48. The -335 speed grade will operate with
128MB, 256MB, 512MB (x64, SR)
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic high or logic low.
= 40ns and
frequency.
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
F
is “worst case.”
DD
t
RAS (MAX) = 120,000ns at any slower
200-PIN DDR SODIMM
2
F
, I
DD
2
N
, and I
©2004 Micron Technology, Inc. All rights reserved.
DD
2
Q
are similar,
t
RAS (MIN)