MT16LSDT3264AG-13EG3 Micron Technology Inc, MT16LSDT3264AG-13EG3 Datasheet - Page 6

• Manufacturer Part Number: MT16LSDT3264AG-13EG3
• Description: MODULE SDRAM 256MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDT3264AG-13EG3

• Memory Type: SDRAM
• Memory Size: 256MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
09005aef80bccbe7
SD8_16C16_32x64AG.fm - Rev. E 12/05 EN
28–29, 46–47, 112–
102, 110, 124, 133,
149–151, 153–156,
65–67, 69–72, 74–
33, 34, 35, 36, 37,
38, 117, 118, 119,
49, 59, 73, 84, 90,
19–20, 55–58, 60,
77, 86–89, 91–95,
97–101, 103–104,
2–5, 7–11, 13–17,
6, 18, 26, 40, 41,
42, 79, 125, 163
30, 45, 114, 129
PIN NUMBERS
139–142, 144,
120, 121, 123
143, 157, 168
113, 130–131
27, 115, 111
165–167
158–161
63, 128
39, 122
83
82
Pin Descriptions
SYMBOL
BA0, BA1
CK0–CK3
DQMB0–
SA0–SA2
S0#–S3#
DQMB7
A0–A11
RAS#,
CAS#,
CKE0,
DQ63
DQ0–
CKE1
WE#
SDA
V
SCL
DD
Output
Output
Supply
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Clock: CK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CK. CK also increments the internal burst counter and
controls the output registers.
Clock Enable: CKE0 activate (HIGH) and deactivate (LOW) the CK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all device banks idle), ACTIVE POWER-DOWN (row ACTIVE in any
device bank) or CLOCK SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode.
The input buffers, including CK, are disabled during power-down and self
refresh modes, providing low standby power.
Chip Select: S# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when S# is registered HIGH. S# is
considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQMB is
sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which device bank the ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to once device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect
data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to configure the presence-
detect device.
Data I/O: Data bus.
Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer
addresses and data into and data out of the presence-detect portion of the
module.
Power Supply: +3.3V ±0.3V.
6
128MB (x64, SR), 256MB (x64, DR)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
168-PIN SDRAM UDIMM
©2003, 2004 Micron Technology, Inc. All rights reserved.