MA330012 Microchip Technology, MA330012 Datasheet - Page 55

• Manufacturer Part Number: MA330012
• Description: MODULE DSPIC33 100P TO 84QFP
• Manufacturer: Microchip Technology

Specifications of MA330012

• Accessory Type: Plug-In Module (PIM) 80p - dsPIC33FJ256GP710
• Kit Contents: DsPIC33 GP 100P To 80P TQFP Plug-In Module
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Silicon Manufacturer: Microchip
• Core Architecture: DsPIC
• Core Sub-architecture: DsPIC33
• Silicon Core Number: DsPIC33F
• Silicon Family Name: DsPIC33FJxxGPxxx
• Rohs Compliant: Yes
• For Use With: DsPICDEM 80-Pin Starter Board (DM300019)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: dsPICDEM (DM300019)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 3-8:
TABLE 3-9:
TABLE 3-10:
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
I2C2RCV
I2C2TRN
I2C2BRG
I2C2CON
I2C2STAT
I2C2ADD
I2C2MSK
Legend:
QEICON
DFLTCON
POSCNT
MAXCNT
Legend:
SFR Name
SFR Name
Name
SFR
u = uninitialized bit, — = unimplemented, read as ‘0’
Addr
01E0 CNTERR
01E2
01E4
01E6
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
.
Addr
0200
0202
0204
0206
0208
020A
020C
Addr
021A
021C
SFR
SFR
0210
0212
0214
0216
0218
Bit 15
QEI REGISTER MAP
I2C1 REGISTER MAP
I2C2 REGISTER MAP
—
ACKSTAT
ACKSTAT
Bit 15
I2CEN
Bit 15
I2CEN
—
—
—
—
—
—
—
—
—
—
Bit 14
—
—
TRSTAT
TRSTAT
Bit 14
Bit 14
QEISIDL
—
—
—
—
—
—
—
—
—
—
—
—
Bit 13
—
I2CSIDL
I2CSIDL
Bit 13
Bit 13
Bit 12 Bit 11
INDX
—
—
—
—
—
—
—
—
—
—
—
—
—
UPDN
SCLREL
SCLREL
Bit 12
Bit 12
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 10
IMV<1:0>
IPMIEN
IPMIEN
Bit 11
Bit 11
—
—
—
—
—
—
QEIM<2:0>
—
—
—
—
—
—
Bit 9
Bit 10
A10M
Bit 10
A10M
BCL
BCL
—
—
—
—
—
—
—
—
—
—
CEID
Bit 8
Maximum Count<15:0>
Position Counter<15:0>
DISSLW
GCSTAT
GCSTAT
QEOUT
DISSLW
SWPAB PCDOUT
Bit 9
Bit 9
Bit 7
—
—
—
—
—
—
ADD10
SMEN
ADD10
Bit 8
SMEN
Bit 8
Bit 6
—
—
—
—
QECK<2:0>
IWCOL
GCEN
TQGATE
IWCOL
GCEN
Bit 7
Bit 7
Bit 5
STREN
STREN
I2COV
I2COV
Bit 6
Bit 6
Bit 4
TQCKPS<1:0>
Address Mask Register
Address Mask Register
ACKDT
ACKDT
Baud Rate Generator Register
Baud Rate Generator Register
Address Register
Address Register
Bit 5
Bit 5
D_A
D_A
Bit 3
—
ACKEN
ACKEN
Transmit Register
Receive Register
Transmit Register
Bit 4
Receive Register
Bit 4
POSRES TQCS UPDN_SRC 0000 0000 0000 0000
P
P
Bit 2
—
RCEN
RCEN
Bit 3
Bit 3
Bit 1
S
S
—
Bit 2
R_W
Bit 2
R_W
PEN
PEN
Bit 0
—
RSEN
RSEN
Bit 1
RBF
Bit 1
RBF
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
Reset State
Bit 0
SEN
Bit 0
TBF
SEN
TBF
Resets
Resets
0000
00FF
0000
1000
0000
0000
0000
0000
00FF
0000
1000
0000
0000
0000
All
All