DLP-FPGA-M DLP Design Inc, DLP-FPGA-M Datasheet - Page 3

• Manufacturer Part Number: DLP-FPGA-M
• Description: MODULE USB-TO-FPGA TOOL W/MANUAL
• Manufacturer: DLP Design Inc

Specifications of DLP-FPGA-M

• Main Purpose: Interface, USB to FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: FT2232D, XC3S250E-4TQ144
• Primary Attributes: USB to FPGA, 40 I/O Pins, SRAM: 128k x 8
• Secondary Attributes: 4 Labs in Manual, 250k System Gates, 5.5k Logic Cells
• Interface Type: USB, SPI
• Product: Interface Modules
• For Use With/related Products: XC3S250E-4TQ144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 813-1009

Chapter 4: Lab 3: Memory Test: Block Diagram, DCM Design, SRAM State Machine, Bi-Directional
Buffers, Test Failed Indicator, User Constraint File, Synthesize the Memory Test Design, Simulate the
Memory Test Design, Implementing the Design, Download the Design to the FPGA
Chapter 5: Lab 4: USB Loopback: Initial Design, USB State Machine Module, Language Template,
Bi-Directional Buffers, Synthesize, Simulate, Pin Constraints, Implement, Download the Design to the
FPGA
(The completed design files for each lab are available for download from the DLP Design website
upon purchase of the DLP-FPGA and Lab Manual.)
3.0 FPGA SPECIFICATIONS
The FPGA device used on the DLP-FPGA is the Xilinx Spartan 3E:
4.0 BITLOADAPP SOFTWARE
Windows software is provided for use with the DLP-FPGA that will load an FPGA configuration (.bit)
file directly to the SPI Flash device via the USB interface. This app (shown below) will allow the user
to erase the flash, verify the erasure and then program and verify the flash:
Rev. 1.4 (November 2010)
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Part Number: XC3S250E
System Gates: 250K
Equivalent Logic Cells: 5,508
CLB Array
Distributed RAM Bits: 38K
Block RAM Bits: 216K
Dedicated Multipliers: 12
DCM’s: 4
o Rows: 34
o Columns: 26
o Total CLB’s: 612
o Total Slices: 2,448
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XC3S250E-4TQ144
© DLP Design, Inc.
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