ISL55100AEVAL3Z Intersil, ISL55100AEVAL3Z Datasheet

ISL55100AEVAL3Z

Manufacturer Part Number

ISL55100AEVAL3Z

Description

EVALUATION BOARD FOR ISL55100A

Manufacturer

Intersil

Datasheets

1.ISL55100AIRZ-T.pdf (14 pages)

2.ISL55100AEVAL3Z.pdf (11 pages)

Specifications of ISL55100AEVAL3Z

Main Purpose

Embedded

Utilized Ic / Part

Primary Attributes

Secondary Attributes

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Current page: 1 of 14
Download datasheet (492Kb)

Quad 18V Pin Electronics Driver/Window

Comparator

The ISL55100A is a Quad pin driver and window comparator

fabricated in a wide voltage CMOS process. It is designed

specifically for Test During Burn In (TDBI) applications,

where cost, functional density, and power are all at a

premium.

This IC incorporates four channels of programmable drivers

and window comparators into a small 72 Ld QFN package.

Each channel has independent driver levels, data, and high

impedance control. Each receiver has dual comparators

which provide high and low threshold levels.

The ISL55100A uses differential mode digital inputs, and can

therefore mate directly with LVDS or CML outputs. Single

ended logic families are handled by connecting one of the

digital input pins to an appropriate threshold voltage (e.g.,

1.4V for TTL compatibility). The comparator outputs are

single-ended, and the output levels are user defined to mate

directly with any digital technology.

The 18V driver output and receiver input ranges allow this

device to interface directly with TTL, ECL, CMOS (3V, 5V,

and 7V), LVCMOS, and custom level circuitry, as well as the

high voltage (Super Voltage) level required for many special

test modes for Flash Devices.

Functional Block Diagram

QB(0:3)

QUAD - WIDE RANGE, LOW ROUT, TRI-STATEABLE - DRIVERS

QA(0:3)

DRVEN+(0:3)

DRVEN-(0:3)

QUAD - DUAL LEVEL COMPARATOR - RECEIVERS

DATA+(0:3)

COMP HIGH

COMP LOW

COMP HIGH

COMP LOW

DATA-(0:3)

Data Sheet

VH(0:3)

DOUT(0:3)

VL(0:3)

CVA(0:3)

VINP(0:3)

CVB(0:3)

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Features

• Low Driver Output Resistance

• 18V I/O Range

• 50MHz Operation

• 4-Channel Driver/Receiver Pairs with Per Pin Flexibility

• Dual Level - Per Pin - Input Thresholds

• Differential or Single-Ended Digital Inputs

• User Defined Comparator Output Levels

• Low Channel-to-Channel Timing Skew

• Small Footprint (72 Ld QFN)

• Pb-Free (RoHS Compliant)

Applications

• Burn In ATE

• Wafer Level Flash Memory Test

• LCD Panel Test

• Low Cost ATE

• Instrumentation

• Emulation

• Device Programmers

Ordering Information

ISL55100AIRZ* ISL55100 AIRZ

*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel

specifications

NOTE: These Intersil Pb-free plastic packaged products employ special

Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is RoHS

compliant and compatible with both SnPb and Pb-free soldering

operations). Intersil Pb-free products are MSL classified at Pb-free peak

reflow temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

November 24, 2008

- R

NUMBER

(Note)

PART

OUT

All other trademarks mentioned are the property of their respective owners.

Maximum: ISL55100A 7.0Ω

Intersil (and design) is a registered trademark of Intersil Americas Inc.

MARKING

PART

-40 to +85

RANGE

TEMP.

(°C)

ISL55100A

72 Ld QFN

PACKAGE

(Pb-Free)

FN7486.2

L72.10x10

DWG. #

PKG.

Related parts for ISL55100AEVAL3Z

ISL55100AEVAL3Z Summary of contents

Page 1

... All other trademarks mentioned are the property of their respective owners. ISL55100A FN7486.2 Maximum: ISL55100A 7.0Ω TEMP. PART RANGE PACKAGE MARKING (°C) (Pb-Free) - QFN Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved PKG. DWG. # L72.10x10 ...

Page 2

Pinout DATA DATA DRV EN DRV EN DATA DATA DRV EN ...

Page 3

Pin Descriptions PIN DATA+(0:3) Positive differential digital input that determines the driver output state when it is enabled. DATA-(0:3) Negative differential digital input that determines the driver output state when it is enabled. DRV EN+(0:3) Positive differential digital input that ...

Page 4

... Disable (HIZ) Time 4 ISL55100A Thermal Information Thermal Resistance (Typical, Notes QFN Package Maximum Junction Temperature (Plastic Package +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C - 0.5V 0.5V) Pb-Free Reflow Profile .see link below CC http://www.intersil.com/pbfree/Pb-FreeReflow.asp MIN SYMBOL (Note 10 (Note (Note 7) ...

Page 5

Electrical Specifications Test Conditions: V LOWSWING = V PARAMETER Enable Time ISL55100A Rise/Fall Times (Note 4) ISL55100A Rise/Fall Times (Note 4) ISL55100A Maximum Toggle Frequency ISL55100A Min Driver Pulse Width ISL55100A Overshoot Lowswing Mode (Note 4) RECEIVER DC CHARACTERISTICS Input ...

Page 6

Electrical Specifications Test Conditions: V LOWSWING = V PARAMETER POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS V Positive Supply Current Negative Supply Current V Supply Current EXT NOTES: 4. Lab characterization, room temp, Timing Parameters Matched Stimulus/Loads, Channel to Channel Skew < ...

Page 7

Test Circuits and Waveforms DRV EN- DRV EN+ (FOR DATA = 0) (FOR DATA = 1) FIGURE 3. DRIVER ENABLE AND DISABLE TIME MEASUREMENT POINTS VINP QX FIGURE 5. RECEIVER PROPAGATION DELAY MEASUREMENT POINTS Application Information The ISL55100A provides Quad ...

Page 8

COMP LOW. These two inputs are unbuffered supply pins, so the sources driving these pins must provide adequate current for the expected load. COMP HIGH and COMP LOW typically connect to the power supplies of the logic ...

Page 9

Power Dissipation Considerations Specifying continuous data rates, driver loads and driver level amplitudes are key in determining power supply requirements as well as dissipation/cooling necessities. Driver Output patterns also impact these needs. The faster the pin activity, the greater the ...

Page 10

VCC DATA+ DATA- VEE VCC DRVEN+ DRVEN- VEE COMP HIGH VCC QA VEE COMP LOW COMP HIGH VCC QB VEE COMP LOW FIGURE 6. ESD STRUCTURE BLOCK DIAGRAM 10 ISL55100A VCC VCC VOH VCC VEE DOUT VCC VEE VOL VEE ...

Page 11

... VL (0.0V FIXED DRIVER SINKS 200mA OUT 2.5 2.0 1.5 1.0 0.5 0 VOLTS (VL = 0.0) FIGURE 11 RAIL OUT 11 ISL55100A Device installed on Intersil ISL55100A Evaluation Board. V 12 3 LOWSWING OFF LOWSWING ON 0 FIGURE 8. DRIVER WAVEFORMS UNDER VARIOUS LOADS DRIVER OUT ...

Page 12

... FREQUENCY (Hz) FIGURE 17. DEVICE POWER DISSIPATION WITH 18, 12 AND 9 All FOUR PINS MAKING TWO TRANSITIONS PER PERIOD 12 ISL55100A Device installed on Intersil ISL55100A Evaluation Board. (Continued) 2200pF 1000pF 680pF 1k/100pF FIGURE 14. DRIVER AND RECEIVER TPD VARIANCE vs V ...

Page 13

... Typical Performance Curves 0 0 20ns/DIV FIGURE 19. FREQUENCY OF 10MHz = 50ns PATTERN RATE 13 ISL55100A Device installed on Intersil ISL55100A Evaluation Board. (Continued 6 3 FIGURE 20. MINIMUM PULSE WIDTH VH 6/8/10V V 12.0 VH 6/8/ 3.0 VL 0.0 EE 10ns/DIV FN7486.2 November 24, 2008 ...

Page 14

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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