CLINK3V48BT-133 National Semiconductor, CLINK3V48BT-133 Datasheet - Page 13

• Manufacturer Part Number: CLINK3V48BT-133
• Description: BOARD EVAL FOR DS90CR485, 486
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-133

• Main Purpose: Interface, SerDes (Serializer / De-Serializer)
• Embedded: No
• Utilized Ic / Part: DS90CR485, DS90CR486
• Primary Attributes: Serializes 48 LVCMOS/LVTTL to 8 LVDS, 66 ~ 133 MHz
• Secondary Attributes: Transmits over 2 Meter 3M MDR LVDS Cable
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

trace layout. The transmitter-DS90CR485 “DS_OPT” pin may
be set high. In a backplane application with short PCB dis-
tance traces, pre-emphasis from the transmitter is typically
not required. The “PRE” pin should be left open (do not tie to
ground). A resistor pad provision for a pull up resistor to Vcc
can be implemented in case pre-emphasis is needed to coun-
teract heavy capacitive loading effects.
SUPPLY BYPASS RECOMMENDATIONS
Bypass capacitors must be used on the power supply pins.
Different pins supply different portions of the circuit, therefore
capacitors should be nearby all power supply pins except as
noted in the pin description table. Use high frequency ceramic
(surface mount recommended) 0.1μF capacitors close to
each supply pin. If space allows, a 0.01μF capacitor should
be used in parallel, with the smallest value closest to the de-
vice pin. Additional scattered capacitors over the printed cir-
cuit board will improve decoupling. Multiple (large) via should
be used to connect the decoupling capacitors to the power
plane. A 4.7 to 10μF bulk cap is recommended near the
PLLVCC pins and also the LVDSVCC pins. Connections be-
tween the caps and the pin should use wide traces.
RECEIVER OUTPUT DRIVE STRENGTH
The DS90CR486 output specifies a 8pF load, V
are tested at ± 2mA, which is intended for only 1 or maybe 2
loads. The DS90CR486 reciever’s output driving capability
has improved over prior generation of Channel Link devices.
OH
and V
OL
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Additional buffering at the reciver output is not necessary. If
high fan-out is required or long transmission line driving ca-
pability, buffering the receiver output is recommended. Re-
ceiver outputs do not support / provide a TRI-STATE function.
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
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For more information:
Channel Link Applications Notes currently available:
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Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
— S = space between the pair
— 2S = space between pairs
— 3S = space to TTL signal
Minimize the number of VIA
Use differential connectors when operating above
500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Minimize skew between pairs
Terminate as close to the RXinputs as possible
AN-1041 Introduction to Channel Link
AN-1108 PCB and Interconnect Guidelines
AN-905 Differential Impedance
National’s LVDS Owner’s Manual
www.national.com