CLINK3V48BT-133 National Semiconductor, CLINK3V48BT-133 Datasheet - Page 3

• Manufacturer Part Number: CLINK3V48BT-133
• Description: BOARD EVAL FOR DS90CR485, 486
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-133

• Main Purpose: Interface, SerDes (Serializer / De-Serializer)
• Embedded: No
• Utilized Ic / Part: DS90CR485, DS90CR486
• Primary Attributes: Serializes 48 LVCMOS/LVTTL to 8 LVDS, 66 ~ 133 MHz
• Secondary Attributes: Transmits over 2 Meter 3M MDR LVDS Cable
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CLHT
CHLT
RCOP
RCOH
RCOL
RSRC
RHRC
RPDL
RPLLS
RPDD
RSKMD
RDR
Symbol
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 1: The I
Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 3: Typical values are given for V
Note 4: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
Note 5: CLHT and CHLT are measurements of the receiver data outputs low-to-high and high-to-low time over the recommended frequency range. The limits
are based on bench characterization and Guaranteed By Design (GBD) using statistical analysis.
Note 6: Receiver Skew Margin with Deskew (RSKMD) is defined as the valid data sampling region at the receiver inputs. The DESKEW function will constrain
the receiver’s sampling strobes to the middle half of the LVDS bit and removes (adjusts for) fixed interconnect skew. This margin (RSKMD) allows for inter-symbol
interference (dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance, and LVDS clock jitter (TJCC).
RSKMD
≥
ISI + TPPOS(variance) + LVDS Source Clock Jitter (cycle to cycle). See Applications Information section for more details.
LVCMOS/LVTTL Low-to-High Transition Time, (Figure 2), Rx
data out, (Note 5)
LVCMOS/LVTTL Low-to-High Transition Time, (Figure 2), Rx
clock out, (Note 5)
LVCMOS/LVTTL High-to-Low Transition Time, (Figure 2), Rx
data out, (Note 5)
LVCMOS/LVTTL High-to-Low Transition Time, (Figure 2), Rx
clock out, (Note 5)
RxCLK OUT Period, (Figure 3)
RxCLK OUT High Time, (Figure 3)
RxCLK OUT Low Time, (Figure 3)
RxOUT Data valid before RxCLK OUT, (Figure
3)
RxOUT Data valid after RxCLK OUT, (Figure
3)
Receiver Propagation Delay - Latency, (Figure 4)
Receiver Phase Lock Loop Set ,(Figure 5)
Receiver Powerdown Delay, (Figure 6)
Receiver Skew Margin with Deskew, BAL=Low
(Figure 7), (Note 6)
Receiver Deskew Range
IN
parameter for the PD pin is not tested at 2.5V.
TH
, V
TL
and ΔV
ID
).
CC
= 3.3V and T
Parameter
A
= +25°C.
f = 133 MHz
f = 100 MHz
f = 66 MHz
f = 133 MHz
f = 100 MHz
f = 66 MHz
f = 133 MHz
f = 100 MHz
f = 66 MHz
f = 133 MHz
f = 100 MHz
f = 66 MHz
f = 133 MHz
f = 100 MHz
f = 66 MHz
f = 133 MHz
f = 100 MHz
f = 66 MHz
3
2(TCIP)+5
7.518
−150
−200
−200
Min
275
400
500
2.7
3.8
6.0
2.7
3.8
6.0
2.0
3.0
5.0
2.5
3.5
6.0
2(TCIP)+10
Typ
0.8
0.7
0.9
0.8
3.5
4.7
7.0
4.1
5.0
8.0
T
2(TCIP)+15
15.152
+150
+200
+200
Max
1.3
1.0
1.3
1.0
10
1
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Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ps
ps
ps
ps
ps
ps