ISL6308AEVAL1Z Intersil, ISL6308AEVAL1Z Datasheet
ISL6308AEVAL1Z
Specifications of ISL6308AEVAL1Z
Related parts for ISL6308AEVAL1Z
ISL6308AEVAL1Z Summary of contents
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... CRZ ISL6308AIRZ* (Note) 6308A IRZ ISL6308AEVAL1Z Evaluation Platform *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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Pinout 3PH 2PH DAC REF OFST VCC COMP FB VDIFF RGND 2 ISL6308A ISL6308A (40 LD 6x6 QFN) TOP VIEW GND ...
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Block Diagram ICOMP DROOP ISEN AMP ISUM IREF RGND VSEN x1 x1 VDIFF UVP OVP OVP +150mV x 0.82 REF1 DAC REF0 DAC REF E/A FB COMP OFST OFFSET 3 ISL6308A OCSET PGOOD OVP 100µA OC +1V SOFT-START AND FAULT ...
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Typical Application - ISL6308A FB VDIFF VSEN RGND 3PH +5V 2PH VCC OFST FS DAC ISL6308A REF REF1 REF0 OVP PGOOD +12V GND ENLL IREF DROOP OCSET ICOMP 4 ISL6308A +12V COMP PVCC1 BOOT1 UGATE1 PHASE1 ISEN1 LGATE1 +12V PVCC2 ...
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... Thermal Resistance QFN Package (Notes Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C = 12V) Pb-Free Reflow Profile .see link below BOOT-PHASE - 0. 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp BOOT + 0.3V BOOT TEST CONDITIONS I ; ENLL = high VCC I ; ENLL = high; all gate outputs open, ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER Maximum External Reference (Note 4) OFS ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER Lower Drive Sink Resistance OVER-TEMPERATURE SHUTDOWN ...
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Functional Pin Description VCC (Pin 6) Bias supply for the IC’s small-signal circuitry. Connect this pin to a +5V supply and locally decouple using a quality 1.0µF ceramic capacitor. PVCC1, PVCC2, PVCC3 (Pins 33, 24, 18) Power supply pins for ...
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OFST (Pin 5) The OFST pin provides a means to program a DC current for generating an offset voltage across the resistor between FB and VDIFF. The offset current is generated via an external resistor and precision internal voltage references. ...
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7A/DIV 7A/DIV L3 PWM3, 5V/DIV PWM2, 5V/DIV I , 7A/DIV L1 PWM1, 5V/DIV FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER To understand the reduction of ripple current ...
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... Channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current- balance method is illustrated in Figure 3, with error correction for channel 1 represented. In the figure, the cycle ...
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... DAC or the external voltage reference) and offset errors in the OFS current source, remote sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6308A to include the combined tolerances of each of these elements, except when an external reference or voltage divider is used, then the tolerances of these components has to be taken into account ...
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EXTERNAL CIRCUIT ISL6308A INTERNAL CIRCUIT COMP VID DAC DAC REF C REF OFS I OFS - VDIFF VSEN OUT - RGND DROOP - V DROOP ...
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By simply adjusting the value the load line can be set to S any level, giving the converter the right amount of droop at all load currents. It may also be necessary to compensate for any changes ...
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PHASE node. This reduces voltage stress on the boot to phase pins. The bootstrap capacitor must have a maximum voltage rating above PVCC + 5V and its capacitance value can be chosen from Equation 11: Q ...
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The Output soft-start time begins with a delay SS period equal to 64 switching cycles after the ENLL has exceeded its POR level, followed by a ...
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The ISL6308A constantly monitors the difference between the VSEN and RGND voltages to detect if an overvoltage event occurs. Before, and during soft-start, while the DAC/REF is ramping up, the overvoltage trip level is V successful soft-start, the overvoltage trip ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for many applications. ...
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At turn on, the upper MOSFET begins to conduct and this transition occurs over a time Equation 17, the 2 approximate power loss UP,2 ⎛ ⎞ ⎛ ⎞ ≈ ...
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The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive ...
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Figure 18. Follow the steps below to ensure the R-C and inductor L/DCR time constants are matched accurately. 1. Capture a transient event with the oscilloscope set to about L/DCR/2 (sec/div). For example, ...
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Case 3: F > -------------------------------- - ⋅ ⋅ 0 2π C ESR ⋅ ⋅ 2π OSC ⋅ ----------------------------------------------- ⋅ ⋅ 0. ⋅ ⋅ 0.66 V ESR ...
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Phase margin is the difference between the closed loop phase at F 0dB equations that follow relate the compensation network’s poles, zeros and gain to the components ( Figure 20 ...
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⎛ ⎞ log ------- - ⎝ ⎠ LOG FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN respond. Because it has a ...
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SWITCHING FREQUENCY (Hz) FIGURE 23 SWITCHING FREQUENCY FS Input Capacitor Selection The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. ...
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PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying channel current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 28 ...