LMH6518SQEVK National Semiconductor, LMH6518SQEVK Datasheet - Page 22

• Manufacturer Part Number: LMH6518SQEVK
• Description: KIT EVAL FOR LMH6518 VGA
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LMH6518SQEVK

• Channels Per Ic: 1 - Single
• Amplifier Type: Variable Gain
• Output Type: Differential
• -3db Bandwidth: 900MHz
• Operating Temperature: -40°C ~ 85°C
• Current - Supply (main Ic): 210mA
• Voltage - Supply, Single/dual (±): 4.75 V ~ 5.25 V
• Board Type: Fully Populated
• Utilized Ic / Part: LMH6518
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• Slew Rate: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

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From Figure 6, the signal path consists of the input impedance
switch, the attenuator switch, Low Noise Amplifier (LNA,
JFET amplifier) to drive the LMH6518 input (+IN), and the
DAC to provide offset adjust. The LNA must have the follow-
ing characteristics:
•
•
•
•
•
•
The undriven input (−IN) is biased to V
driver. The impedance driving the LMH6518’s −IN should be
closely matched to the LNA’s output impedance for good set-
tling time performance.
Appendix A shows one possible implementation of the LNA
buffer along with performance data.
When the LMH6518’s Auxiliary output is not used, it is possi-
ble to disable this output using SPI-1 (see “Logic Functions”
CS
SCLK
SDIO
Set U1’s common mode level to V
Very low drift (1 mV shift at LNA output could translate into
88 mV shift at LMH6518 output at max gain, or
FS).
Low output impedance (
settling behavior
Low Noise (<0.98 nV/
LMH6518 Noise Figure. Note that Figure 6 does not show
the necessary capacitors across the resistors in the front-
end attenuators (see Figure 15). These capacitors provide
frequency response compensation and limit the noise
contribution from the resistors so that they do not impact
the signal path noise. For more information about front-
end attenuator design, including frequency compensation,
see the Reference section for additional resources.
Gain of 1 V/V (or very close to 1 V/V)
Excellent frequency response flatness from DC to >
500-800 MHz to not impact the time domain performance
Pin Name
Input
Input
Input-Output
≤
) to reduce the impact on the
50Ω) to drive U1, for good
Type
CC
/2 (
CC
/2 using a voltage
∼
2.5V)
Serial Chip Select: While this signal is asserted SCLK is used to accept serial data
present on SDIO and to source serial data on SDIO. When this signal is de-
asserted, SDIO is ignored and SDIO is in TRI-STATE
Serial Clock: Serial data are shifted into and out of the device synchronous with
this clock signal. SCLK transitions with CS de-asserted are ignored. SCLK to be
stopped when not needed to minimize digital crosstalk.
Serial Data-In or Data-out: Serial data are shifted into the device (8 bit Command
and 16 bit Data) on this pin while CS signal is asserted during Write operation.
Serial data are shifted out of the device on this pin during a read operation while
CS signal is asserted. At other times, and after one complete Access Cycle (24 bits,
see Figure 8 and Figure 9), this input is ignored. This output is in TRI-STATE mode
when CS is de-asserted. This pin is bi-directional.
TABLE 3. SPI-1 Pin Descriptions
∼
13% of
22
section for SPI register map). The Electrical Characteristic
Table shows that by doing so, device power dissipation de-
creases by the reduction in supply current of about 60 mA. As
can be seen in Figure 7, in the absence of heavy common
loading, the Auxiliary output will be at a voltage close to 1.7V
(V
will also increase and it is important to make sure any circuitry
tied to this output is capable of handling the 2.3V possible
under V
FIGURE 7. Auxiliary Output Voltage as a Function of V
LOGIC FUNCTIONS
The following LMH6518 functions are controlled using the
SPI-1 compatible bus:
•
•
•
•
•
The SPI-1 bus uses 3.3V logic. “SDIO” is the serial digital in-
put-output which can write to the LMH6518 or read back from
it. “SCLK” is the bus clock with chip select function controlled
by “CS”
CC
Filters (20, 100, 200, 350, 650, 750 MHz or full bandwidth)
Power Mode (Full Power or Auxiliary Hi-Z (high
impedance)
Preamp (HG or LG)
Attenuation Ladder (0-20 dB, 10 states)
LMH6518 state “Write” or “Read” back
= 5V). With higher supply voltages, the Auxiliary voltage
Function and Connection
CC
worst case condition of 5.5V.
®
mode.
30068862
CC