LMH6518SQEVK National Semiconductor, LMH6518SQEVK Datasheet - Page 26

• Manufacturer Part Number: LMH6518SQEVK
• Description: KIT EVAL FOR LMH6518 VGA
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LMH6518SQEVK

• Channels Per Ic: 1 - Single
• Amplifier Type: Variable Gain
• Output Type: Differential
• -3db Bandwidth: 900MHz
• Operating Temperature: -40°C ~ 85°C
• Current - Supply (main Ic): 210mA
• Voltage - Supply, Single/dual (±): 4.75 V ~ 5.25 V
• Board Type: Fully Populated
• Utilized Ic / Part: LMH6518
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• Slew Rate: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

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Trigger. The result could be a loss of Trigger pulse and/or
visual distortion of the displayed waveform. To avoid this sce-
nario, the oscilloscope should detect an excessive overdrive
and go into trigger-loss mode. Done this way, the oscilloscope
display would show the last waveform that did not violate the
overdrive condition. Preferably there would be a visual indi-
cator on the screen that alerts the user of the situation so that
CIRCUIT OPERATION
This circuit uses an N-Channel JFET (J10) in Source-Follow-
er configuration, to buffer the input signal, with J8 acting as a
constant current source. This buffer presents a fixed input
impedance (1 MΩ||10 pF) with a gain close to 1 V/V.
The signal path is AC coupled through C
frequency) at LMH6518 +IN maintained through the action of
U1. NPN transistor Q0 is an emitter follower which isolates
the buffer from the load (LMH6518 input and board traces).
The undriven input of the LMH6518, −IN, is biased to 2.5V by
R
and the upper ½ of U1 compares it to the combination of the
driven output level at LMH6518 +IN and the scaled version of
scope input at R
cordingly to set the LMH6518 +IN. This control loop has a
frequency response that covers DC to a few Hz, limited by the
roll-off capacitor C
mation). DC and low frequency gain is given by:
With the values in Figure 13
6
, R
9
voltage divider. The Lower ½ of U1 inverts this voltage
14
3
, R
and R
21
junction, and adjusts J10 Gate ac-
15
→
combination (1
R
2
≈
452 kΩ: .
7
with DC (and low
FIGURE 13. JFET LNA Implementation
st
order approxi-
26
he can correct the excessive condition to return to normal
display.
APPENDIX A
Here is the schematic drawing for a possible implementation
of the LNA buffer shown in Figure 6:
For a flat frequency response, the DC (low frequency) gain
needs to be lowered to match the less-than-1 V/V AC (high
frequency) path gain through the JFETs. This can be done by
increasing the value of R
By choosing the values of R
the frequency response at J10 Gate (and consequently the
output) will remain flat when C
rection is done by varying the voltage at R
equivalent as shown, in order to shift the LMH6518 +IN volt-
age relative to −IN. The result is a circuit which shifts the
ground referenced scope input to 2.5V (V
justable offset and without any JFET or BJT related offsets.
Note that the front-end attenuator (not shown) lower leg re-
sistance should be increased for proper divider-ratio to ac-
count for the 1 MΩ shunt due to the series combination of
R
be formed by a series 900 kΩ and a shunt 111 kΩ for a scope
BNC input impedance of 1 MΩ (= 900K + (111K || 1M)).
21
and R
14
. For example, a 10:1 front-end attenuator could
2
.
15
7
and R
starts to conduct. Offset cor-
11
so that
CC
4
, using a DAC or
/2) CM with ad-
30068835