LMH6518SQEVK National Semiconductor, LMH6518SQEVK Datasheet - Page 4

• Manufacturer Part Number: LMH6518SQEVK
• Description: KIT EVAL FOR LMH6518 VGA
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LMH6518SQEVK

• Channels Per Ic: 1 - Single
• Amplifier Type: Variable Gain
• Output Type: Differential
• -3db Bandwidth: 900MHz
• Operating Temperature: -40°C ~ 85°C
• Current - Supply (main Ic): 210mA
• Voltage - Supply, Single/dual (±): 4.75 V ~ 5.25 V
• Board Type: Fully Populated
• Utilized Ic / Part: LMH6518
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• Slew Rate: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

www.national.com
V
V
V
V
Z
V
V
V
TCV
I
V
V
TC_V
BAL_Error_DC
BAL_Error_AC
PB
PSRR
PSRR_CM
V
V
Digital I/O & Timing
V
V
V
V
R
I_in
F
F
T
T
T
t
T
B
CDS
OUT_DIFF
SCLK
SCLK_DT
S
H
CES
IAG
OUT_MAX1
OUT_MAX2
OUT_MAX3
OUT_MAX4
OOS
OOS_shift1
OOS_shift2
OCM
OS_CM
CM_I
CM_AUX_I
IH
IL
OH
OL
Hi_Z
Symbol
OOS
OS_CM
Voltage range at each output pin
(clamped)
Differential Output Impedance
Output Offset Voltage
Output Offset Voltage Shift
Output Offset Voltage Drift
(Note 9)
Input Bias Current
(Note 10)
Output CM Voltage Range
Output CM Offset Voltage
CM Offset Voltage Temp Coefficient
Output Gain Balance Error
Phase Balance Error (See Definition)
Differential Power Supply Rejection
(see Definition)
CM Power Supply Rejection
(see Definition)
V
(Note 10)
V
(Note 10)
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Output Resistance
Input Bias Current
SCLK Rate
SCLK Duty Cyle
SDIO Setup Time
SDIO Hold Time
CS Enable Setup Time
CS Disable Setup Time
Inter-Acess Gap
CM
CM_AUX
Input Bias Current
Input Bias Current
Parameter
Main Output, All gains, V
Auxiliary Output, All Gains,
V
Main Output, All Gains, V
Auxiliary output, All gains,
V
All Gains
All Gains
Preamp LG to Preamp HG
All Gains, Excluding Preamp Step
Preamp HG, 0 dB Ladder
Preamp LG, 0 dB Ladder
All Gains
All Gains
All Gains
250 MHz
Preamp HG, 0 dB Ladder
Preamp HG, 0 dB Ladder
Preamp LG, 0 dB
All Gains
All Gains
High Impedance Mode
From CS asserted to rising edge of
SCLK
From CS de-asserted to rising edge
of SCLK
CM
CM
= 1.2V
= 1.45V
4
Condition
CM
CM
= 1.2V
= 1.45V
(Note 8)
V
DD
0.95
Min
−60
−50
−55
0.5
0.8
92
45
25
25
25
25
3
-0.6
(Note 7)
13.7
12.7
1.20
±0.8
Typ
100
±15
−24
+40
±15
+55
−78
−45
−87
−70
−71
V
−7
±1
±1
<1
50
0
5
DD
(Note 8)
+100
+140
Max
2.05
2.45
1.45
±40
±30
±10
±20
±10
±20
108
1.8
2.2
0.5
10
55
Cycles
µV/°C
µV/°C
SCLK
Units
MHz
deg
MΩ
mV
mV
mV
µA
dB
dB
dB
nA
μA
ns
ns
ns
ns
%
of
Ω
V
V
V
V
V
V