HW-SD1800A-DSP-SB-UNI-G Xilinx Inc, HW-SD1800A-DSP-SB-UNI-G Datasheet - Page 16

• Manufacturer Part Number: HW-SD1800A-DSP-SB-UNI-G
• Description: KIT DEVELOPMENT SPARTAN 3ADSP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr
• Type: DSPr

Specifications of HW-SD1800A-DSP-SB-UNI-G

• Contents: Development Platform, Power Supply and software
• Silicon Manufacturer: Xilinx
• Features: 10/100/1000 PHY, JTAG Programming And Configuration Port
• Silicon Family Name: Spartan-3A
• Silicon Core Number: 3SD1800A-FG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Spartan 3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1574; HW-SD1800A-DSP-DB-UNI-G; HW-SD1800A-DSP-DB-UNI-G; HW-SD1800A-DSP-SB-UNI-G

Functional Description
40
National Semiconductor 10/100/1000 Ethernet PHY
Other interfaces consist of two 0.1” 6-pin headers to accept Digilent plug-in modules, a 7-
pin Serial ATA connector ( this is not a serial ATA interface) to connect to an Eridon debug
module, and a 0.1” 2 x 6 header for SPI interface expansion.
The PHY is a National DP83865DVH Gig PHYTER“ V. The DP83865 is a low power
version of the National Gig PHYTER V with a 1.8V core voltage and 2.5V I/O voltage. The
PHY also supports 3.3V I/O, but the 2.5V option is used on the board. The PHY is
connected to a Tyco-AMP RJ-45 jack with integrated magnetics (part number: 1-6605833-1).
The jack also integrates two LEDs and their corresponding resistors as well as several other
passive components. External logic is used to logically OR the three link indicators for 10,
100 and 1000 Mb/s to drive a Link LED on the RJ-45 jack. The external logic is for the
default strap options and may not work if the strap options are changed. Four more LEDs
are provided on the board for status indication. These LEDs indicate Link at 10 Mb/s, Link
at 100 Mb/s, Link at 1000 Mb/s and Full Duplex operation. The PHY clock is generated
from its own 25 MHz crystal (FOX FX325BS).
Figure 5
Ethernet PHY. The PHY signal connections at the FPGA are listed in
are connected to FPGA Bank 3 which is fixed at +1.8V I/O voltage, necessitating voltage
translation between +1.8V and +2.5V to match the PHY I/O voltage requirements.
X-Ref Target - Figure 5
Spartan
3A DSP
FPGA
shows a high-level block diagram of the interface to the DP83865 Tri-mode
gbe_mclk
gbe_rstn
Figure 5: 10/100/1000 Mb/s Ethernet Interface
www.xilinx.com
National 10/100/1000 PHY
data_tx[7:0]
clk_tx
control_tx
gtxclk
data_rx[7:0]
clk_rx
control_rx
clk_to_MAC
reset#
MDIA_P
MDIA_N
MDIA_P
MDIA_N
MDIA_P
MDIA_N
MDIA_P
MDIA_N
Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
Crystal
25 MHz
LEDs
Table
7. These signals
UG454_05_050908
R