AD9549/PCBZ Analog Devices Inc, AD9549/PCBZ Datasheet
AD9549/PCBZ
Specifications of AD9549/PCBZ
Related parts for AD9549/PCBZ
AD9549/PCBZ Summary of contents
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FEATURES Flexible reference inputs Input frequencies: 8 kHz to 750 MHz Two reference inputs Loss of reference indicators Auto and manual holdover modes Auto and manual switchover modes Smooth A-to-B phase transition on outputs Excellent stability in holdover mode Programmable ...
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AD9549 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Basic Block Diagram ........................................................................ 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 6 Absolute Maximum Ratings ............................................................ 9 Thermal ...
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REVISION HISTORY 12/10—Rev Rev. D Changes to I (Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30, AVDD Pin44, Pin 45) Parameter ................................................................. 4 Changes to Total Power Dissipation Parameter and Added Endnote 4 ........................................................................................... 5 ...
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AD9549 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%. AVSS = 0 V, DVSS = 0 V, unless otherwise noted. Table ...
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Parameter SYSTEM CLOCK INPUT SYSCLK PLL Bypassed Input Capacitance Input Resistance Internally Generated DC Bias Voltage 3 Differential Input Voltage Swing SYSCLK PLL Enabled Input Capacitance Input Resistance Internally Generated DC Bias Voltage 3 Differential Input Voltage Swing Crystal Resonator ...
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AD9549 AC SPECIFICATIONS GHz, DAC kΩ, power supply pins within the range specified in the DC Specifications section, unless otherwise noted. S SET Table 2. Parameter REFERENCE INPUTS Frequency Range (Sine Wave) Frequency Range ...
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Parameter CMOS Output Driver (AVDD3/Pin 37) @ 3.3 V Frequency Range Duty Cycle Rise Time/Fall Time (20-80%) CMOS Output Driver (AVDD3/Pin 37) @ 1.8 V Frequency Range Duty Cycle Rise Time/Fall Time (20% to 80%) HOLDOVER Frequency Accuracy OUTPUT FREQUENCY ...
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AD9549 Parameter LOCK DETECTION Phase Lock Detector Time Threshold Programming Range Time Threshold Resolution Lock Time Programming Range Unlock Time Programming Range Frequency Lock Detector Normalized Frequency Threshold Programming Range Normalized Frequency Threshold Programming Resolution Lock Time Programming Range Unlock ...
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ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Analog Supply Voltage (AVDD Digital Supply Voltage (DVDD Digital I/O Supply Voltage 3.6 V (DVDD_I/O) DAC Supply Voltage (AVDD3 Pins) 3.6 V Maximum Digital Input Voltage −0 ...
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AD9549 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD_I/O REFA_IN REFA_INB AVDD3 REFB_IN REFB_INB NOTES CONNECT. 2. THE EXPOSED THERMAL DIE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST ...
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Input/ Pin No. Output Pin Type 20 Current set resistor 27 I Differential input 28 I Differential input 1.8 V CMOS 33, 39, 43 GND 34 O 1.8 V HSTL ...
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AD9549 Input/ Pin No. Output Pin Type 60 I 3.3 V CMOS 61 I 3.3 V CMOS 62 O 3.3 V CMOS 63 I/O 3.3 V CMOS 64 I 3.3 V CMOS Exposed O GND Die Pad Mnemonic Description IO_UPDATE ...
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TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, AVDD, AVDD3, and DVDD are at nominal supply voltage; f –70 RMS JITTER (12kHz TO 20MHz): 0.18ps RMS JITTER (50kHz TO 80MHz): 0.24ps –80 –90 –100 –110 –120 –130 –140 –150 10 100 1k ...
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AD9549 2.0 1.5 1.0 0 SYSTEM CLOCK PLL INPUT FREQUENCY (MHz) Figure 9. 12 kHz to 20 MHz RMS Jitter vs. System Clock PLL Input Frequency, SYSCLK = 1 GHz 19.44 MHz, f REF ...
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NOM SKEW 25°C, 1.8V SUPPLY SLOW SKEW 90°C, 1.7V SUPPLY 450 0 200 400 FREQUENCY (MHz) Figure 12. HSTL Output Driver Single-Ended Peak-to-Peak Amplitude vs. Toggle Rate (100 Ω Across Differential Pair) 2.5 2.0 1.5 1.0 ...
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AD9549 INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.01µF AD9549 DOWNSTREAM 1.8V 100Ω HSTL OUTPUT 0.01µF Figure 18. AC-Coupled HSTL Output Driver 50Ω AD9549 DOWNSTREAM 1.8V HSTL AVDD/2 OUTPUT 50Ω Figure 19. DC-Coupled HSTL Output Driver DEVICE (HIGH-Z) DEVICE (HIGH-Z) Rev Page ...
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THEORY OF OPERATION REFSELECT REFA_IN REFB_IN INPUT REF MONITOR OOL AND LOR IRQ AND STATUS LOGIC OVERVIEW The AD9549 provides a clocking output that is directly related in phase and frequency to the selected (active) reference (REFA ...
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AD9549 The PFD outputs a time series of digital words that are routed to the digital loop filter. The digital filter implementation offers many advantages: The filter response is determined by numeric coefficients rather than by discrete component values; there ...
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The DCO has a minimum frequency, f DCO[MIN] Output Characteristics section of the AC Specifications table). This minimum frequency imposes a lower bound, S feedback divider value, as well. f DCO [ ...
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AD9549 FREQUENCY TUNING WORD (FTW) The null points imply the existence of transmission zeros placed at finite frequencies. While transmission zeros placed at infinity yield minimal phase delay, zeros placed closer to dc result in increased phase delay. Hence, the ...
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In holdover mode, the AD9549 uses past tuning words when the loop is closed to determine its output frequency. Therefore, the loop must be successfully closed for holdover mode to work. Switching in and out of holdover mode can be ...
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AD9549 Phase Detector Gain Matching Although the fine and coarse phase detectors use different means to make a timing measurement essential that both have equivalent phase gain. Without proper gain matching, the closed-loop dynamics of the system cannot ...
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The three coefficients are implemented as digital elements, necessitating quantized values. Determination of the programmed coefficient values in this context follows. The quantized α coefficient is composed of three factors, where α , α , and α are the programmed ...
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AD9549 The resulting loop filter coefficients for the lower loop bandwidth, along with the necessary programming values, are shown as follows: α = 0.005883404361345 α = 1542 (0x606) 0 α (0x00) 1 α (0x07) 2 β ...
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The phase lock detect signal is generated once the control logic observes that the output of the comparator has been in the true x state for 2 periods of the P-divider clock (see the Digital Loop Filter section for a ...
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AD9549 For example MHz FPFD_Gain = 200, and a fre- R quency lock threshold specified, the frequency lock detect threshold value is = FLDT × × 6 ...
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The following four values are needed to calculate the correct values of the reference monitor: • System clock frequency, f (usually 1 GHz) S • Reference input frequency, f (in Hz) R • Error bound, E (1% = 0.01) • ...
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AD9549 Use of Line Card Mode to Eliminate Runt Pulses When two references are not in exact phase alignment and a transition is made from one to the other possible that an extra pulse may be generated. This ...
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When calculating frequency error for a hitless switchover environment such as Stratum 3, as defined in Telcordia GR-1244-CORE, the designer must consider the frequency error budget for the entire system. The frequency disturbance caused by a reference clock switchover in ...
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AD9549 RESET REFA & 1 HOLDOVER REFA & 3 HOLDOVER REFA: REFERENCE A SELECTED REFB: REFERENCE B SELECTED HOLDOVER: HOLDOVER STATE FAILA: REFERENCE A FAILED FAILB: REFERENCE B FAILED VALIDA: REFERENCE A VALIDATED VALIDB: REFERENCE B VALIDATED Holdover and Reference ...
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Reference Validation Timers Each of the two reference inputs has a dedicated validation timer. The status of these timers is used by the holdover state machine as part of the decision making process for reverting to a previously faulty reference. ...
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AD9549 OUTPUT FREQUENCY RANGE CONTROL Under normal operating conditions, the output frequency is dynamically changing in response to the output of the digital loop filter. The loop filter can steer the DDS to any frequency between dc and f /2 ...
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FDBK_IN INPUTS The feedback pins, FDBK_IN and FDBK_INB, serve as the input to the feedback path of the digital PLL. Typically, these pins are used to receive the signal generated by the DDS after it has been band-limited by the ...
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AD9549 The SYSCLK PLL multiplier path is enabled by a Logic 0 (default) in the PD SYSCLK PLL bit of the I/O register map. The SYSCLK PLL multiplier can be driven from the SYSCLK input pins by one of two ...
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External Loop Filter (SYSCLK PLL) The loop bandwidth of the SYSCLK PLL multiplier can be adjusted by means of three external components, as shown in Figure 44. The nominal gain of the VCO is 800 MHz/V. The recommended component values ...
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AD9549 48-BIT ACCUMULATOR 48 48-BIT 14 48 FREQUENCY TURNING WORD (FTW) SYSCLK CH1 HARMONIC NUMBER CH1 CANCELLATION PHASE OFFSET CH2 HARMONIC NUMBER CH2 CANCELLATION PHASE OFFSET CH1 CANCELLATION MAGNITUDE CH2 CANCELLATION MAGNITUDE The mechanics of performing harmonic spur reduction are ...
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Single-Ended CMOS Output In addition to the high speed differential output clock driver, the AD9549 provides an independent, single-ended output, CMOS clock driver. It serves as a relatively low speed (<150 MHz) clock source. The origin of the signal generated ...
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AD9549 The measurement error (ε) associated with the frequency estimator depends on the choice of the measurement interval parameter (K). These are related by ρK = − ε − floor ρK 1 With a specified fractional error ...
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INTERNAL STATUS FLAGS REFA LOR REFA OOL REFA INVALID REFB LOR REFB OOL REFB INVALID PHASE LOCK DETECT FREQUENCY LOCK DETECT IRQ STATUS AND WARNINGS Status Pins Four pins (S1 to S4) are reserved for providing device status information to ...
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AD9549 The DDS output frequency listed in Table 8 assumes that the internal DAC sampling frequency (f frequencies scale 1:1 with f , meaning that other startup S frequencies are available by varying the SYSCLK frequency. At startup, the internal ...
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THERMAL PERFORMANCE Table 9. Thermal Parameters Symbol Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board θ Junction-to-ambient thermal resistance, 0.0 m/sec air flow per JEDEC JESD51-2 (still air) JA θ Junction-to-ambient thermal resistance, 1.0 m/sec air flow per ...
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AD9549 POWER-UP POWER-ON RESET On initial power-up recommended that the user apply a RESET pulse, at least duration, on Pin 59 after both of the following two conditions are met: • The 3.3 V supply ...
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POWER SUPPLY PARTITIONING The AD9549 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the consumption of each power block varies with frequency. The numbers ...
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AD9549 SERIAL CONTROL PORT The AD9549 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. Single or multiple byte transfers are supported, as well as MSB first or ...
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Read If the instruction word is for a read operation (I15 = 1), the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where ...
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AD9549 Table 11. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 A12 A11 CSB SCLK DON'T CARE SDIO DON'T CARE R A12 A11 A10 A9 A8 16-BIT INSTRUCTION ...
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S CSB t DS SCLK SDIO Table 12. Definitions of Terms Used in Serial Control Port Timing Diagrams Parameter Description t Period of SCLK CLK t Read data valid time (time from falling edge of SCLK to valid data ...
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AD9549 I/O REGISTER MAP All address and bit locations that are left blank in Table 13 are unused. Accessing reserved registers should be avoided. In cases where some of the bits in register are reserved, the user can rely on ...
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Addr 1 (Hex) Type Name Bit 7 0x0108 M Loop coefficients 0x0109 M 0x010A M 0x010B M 0x010C M 0x010D M 0x010E M 0x010F M 0x0110 M 0x0111 M 0x0112 0x0113 0x0114 0x0115 RO FTW estimate 0x0116 RO 0x0117 RO ...
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AD9549 Addr 1 (Hex) Type Name Bit 7 0x01A6 M FTW0 (open-loop 0x01A7 M frequency 0x01A8 M tuning 0x01A9 M word) 0x01AA M 0x01AB M 0x01AC M Phase and (open loop 0x01AD only) Reference selector/holdover 0x01C0 M Automatic control 0x01C1 ...
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Addr 1 (Hex) Type Name Bit 7 0x030E RO HFTW 0x030F RO 0x0310 RO 0x0311 RO 0x0312 RO 0x0313 RO 0x0314 M Phase lock 0x0315 M 0x0316 M 0x0317 M 0x0318 M Phase unlock watchdog timer, 0x0319 M Frequency lock ...
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AD9549 Addr 1 (Hex) Type Name Bit 7 Calibration (user-accessible trim) 0x0400 K-divider 0x0401 0x0402 M CPFD gain 0x0403 M 0x0404 FPFD gain 0x0405 Reserved 0x0406 RO Part Part version version 0x0407 Reserved 0x0408 0x0409 M PFD offset 0x040A M ...
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I/O REGISTER DESCRIPTIONS SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005) Register 0x0000—Serial Configuration Table 14. Bits Bit Name Description [7:4] These bits are the mirror image of Bits[3:0]. 3 Long instruction Read-only. The AD9549 supports only long instructions. 2 ...
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AD9549 Register 0x0011—Reserved Register 0x0012—Reset (Autoclear) To reset the entire chip, the user can also use the (nonself-clearing) soft reset bit in Register 0x0000. Except for IRQ reset, the user normally would not need to use this bit. However, if ...
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Register 0x0023—PFD Divider Table 22. Bits Bit Name Description [3:0] PFD divider Divide ratio for PFD clock from system clock. This is typically varied only in cases where the designer wishes to run the DPLL phase detector fast while SYSCLK ...
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AD9549 Register 0x0104—S-Divider (DPLL Feedback Divider) Table 27. Bits Bit Name [7:0] S-divider Register 0x0105—S-Divider (DPLL Feedback Divider) (Continued) Table 28. Bits Bit Name [15:8] S-divider Register 0x0106—S-Divider (DPLL Feedback Divider) (Continued) Table 29. Bits Bit Name 7 Falling edge ...
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Register 0x010A—Loop Coefficients (Continued) Table 33. Bits Bit Name Description [4:0] Alpha-1 Power-of-2 multiplier for alpha coefficient. Register 0x010B—Loop Coefficients (Continued) Table 34. Bits Bit Name Description [2:0] Alpha-2 Power-of-2 divider for alpha coefficient. Register 0x010C—Loop Coefficients (Continued) Table 35. ...
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AD9549 Register 0x0115—FTW Estimate (Read Only) Table 41. Bit Bit Name Description [7:0] FTW estimate This frequency estimate is from the frequency estimator circuit and is informational only useful for verifying the input reference frequency. See the Frequency ...
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Register 0x011B—FTW Lower Limit Table 47. Bits Bit Name Description [7:0] FTW lower limit Lowest DDS tuning word in closed-loop mode. This feature is recommended when a band-pass reconstruction filter is used. See the Output Frequency Range Control section. Register ...
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AD9549 Register 0x0121—FTW Upper Limit Table 53. Bits Bit Name Description [7:0] FTW upper limit Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass reconstruction filter is used. See the Output Frequency Range Control ...
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FREE-RUN (SINGLE-TONE) MODE (REGISTER 0x01A0 TO REGISTER 0x01AD) Register 0x01A0 to Register 0x01A5—Reserved Register 0x01A6—FTW0 (Frequency Tuning Word) Table 60. Bit Bit Name Description [7:0] FTW0 FTW (frequency tuning word) for DDS when the loop is not closed (see Register ...
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AD9549 Register 0x01AC to Register 0x01AD—Phase Table 66. Bits Bit Name Description [7:0] DDS phase word Allows user to vary the phase of the DDS output. See the Direct Digital Synthesizer section. Register 0x01AC is the least significant byte of ...
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Register 0x01C3—Reference Validation Table 71. Bits Bit Name Description [7:5] Reserved Reserved. [4:0] Validation timer The value in this register sets the time required to validate a reference after an LOR or OOL event before the reference can be used ...
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AD9549 MONITOR (REGISTER 0x0300 TO REGISTER 0x0335) Register 0x0300—Status This register contains the status of the chip. This register is read-only and live update. Table 74. Bits Bit Name Description 7 Reserved Reserved. 6 PFD frequency too high This flag ...
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Register 0x0305—IRQ Mask (Continued) Table 77. Bits Bit Name 4 Frequency estimator done 3 Phase unlock 2 Phase lock 1 Frequency unlock 0 Frequency lock Register 0x0306—IRQ Mask (Continued) Table 78. Bits Bit Name [7:6] Reserved 5 REFA valid 4 ...
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AD9549 Register 0x030C—Control Table 81. Bits Bit Name 7 Enable REFA LOR 6 Enable REFA OOL 5 Enable REFB LOR 4 Enable REFB OOL [3:2] Reserved 1 Enable phase lock detector 0 Enable frequency lock detector Register 0x030D—Reserved Register 0x030E—HFTW ...
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Register 0x0314—Phase Lock Table 88. Bits Bit Name [7:0] Phase lock threshold Register 0x0315—Phase Lock (Continued) Table 89. Bits Bit Name [15:8] Phase lock threshold Register 0x0316—Phase Lock (Continued) Table 90. Bits Bit Name [23:16] Phase lock threshold Register 0x0317—Phase ...
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AD9549 Register 0x031E—Loss of Reference Table 98. Bits Bit Name [7:0] REFA LOR divider Register 0x031F—Loss of Reference (Continued) Table 99. Bits Bit Name [15:8] REFA LOR divider Register 0x0320—Loss of Reference (Continued) Table 100. Bits Bit Name [7:0] REFB ...
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Register 0x0328—Reference OOL (Continued) Table 108. Bits Bit Name Description [7:0] REFA OOL lower limit See the Reference Frequency Monitor section. Register 0x0329—Reference OOL (Continued) Table 109. Bits Bit Name Description [15:8] REFA OOL lower limit See the Reference Frequency ...
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AD9549 Register 0x0332—Reference OOL (Continued) Table 118. Bits Bit Name Description [7:0] REFB OOL lower limit See the Reference Frequency Monitor section. Register 0x0333—Reference OOL (Continued) Table 119. Bits Bit Name Description [15:8] REFB OOL lower limit See the Reference ...
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Register 0x0406—Part Version Table 127. Bits Bit Name Description [7:6] Part version 01b = AD9549, Revision A 00b = AD9549, Revision 0 [5:0] Reserved N/A Register 0x0407 to Register 0x0408—Reserved Register 0x0409—PFD Offset Table 128. Bits Bit Name Description [7:0] ...
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AD9549 Register 0x0500—Spur A Table 133. Bits Bit Name Description 7 HSR-A enable Harmonic Spur Reduction A enable. 6 Amplitude gain × 2 [5:4] Reserved Reserved. [3:0] Spur A harmonic Spur A Harmonic 1 to Spur A Harmonic 15. Register ...
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APPLICATIONS INFORMATION SAMPLE APPLICATIONS CIRCUIT DIFF HSTL OUTPUT CMOS OUTPUT FDBK_IN FDBK_INB INPUT A REF A DDS/ DAC INPUT B REF B AD9549 SYSCLK Applications Circuit Features Features of this applications circuit include the following: • Input frequencies down to ...
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AD9549 OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model 1 Temperature Range AD9549ABCPZ −40°C to +85°C AD9549ABCPZ-REEL7 −40°C to +85°C AD9549A/PCBZ RoHS Compliant Part. 9.10 9.00 SQ 8.90 ...
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NOTES Rev Page AD9549 ...
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AD9549 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06744-0-12/10(D) Rev Page ...