AD9549/PCBZ Analog Devices Inc, AD9549/PCBZ Datasheet - Page 65

• Manufacturer Part Number: AD9549/PCBZ
• Description: BOARD EVALUATION FOR AD9549
• Manufacturer: Analog Devices Inc

Specifications of AD9549/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9549
• Primary Attributes: 2 Inputs, 2 Outputs, VCO
• Secondary Attributes: CMOS, HSTL Output Logic, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register 0x0305—IRQ Mask (Continued)
Table 77.
Bits
4
3
2
1
0
Register 0x0306—IRQ Mask (Continued)
Table 78.
Bits
[7:6]
5
4
3
2
1
0
Register 0x0307—IRQ Mask (Continued)
Table 79.
Bits
[7:6]
5
4
3
2
1
0
Register0x0308—S1 Pin Configuration
See the Status and Warnings section. The choice of input for a given pin must be all REFA or all REFB and not a combination of both.
Table 80.
Bits
7
6
5
4
3
2
1
0
Register 0x0309—S2 Pin Configuration
Same as Register 0x0308, except applies to Pin S2. See Table 80.
Register 0x030A—S3 Pin Configuration
Same as Register 0x0308, except applies to Pin S3. See Table 80.
Register 0x030B—S4 Pin Configuration
Same as Register 0x0308, except applies to Pin S4. See Table 80.
Bit Name
REF?
REF? LOR
REF? OOL
REF? not valid
Phase lock
Frequency lock
Reserved
IRQ
Bit Name
Reserved
REFB valid
!REFB valid
REFB LOR
!REFB LOR
REFB OOL
!REFB OOL
Bit Name
Frequency estimator done
Phase unlock
Phase lock
Frequency unlock
Frequency lock
Bit Name
Reserved
REFA valid
!REFA valid
REFA LOR
!REFA LOR
REFA OOL
!REFA OOL
Description
Trigger IRQ when the frequency estimator is done.
Trigger IRQ on falling edge of phase lock signal.
Trigger IRQ on rising edge of phase lock signal.
Trigger IRQ on falling edge of frequency lock signal.
Trigger IRQ on rising edge of frequency lock signal.
Description
Reserved.
Trigger IRQ on rising edge of Reference A’s valid.
Trigger IRQ on falling edge of Reference A’s valid.
Trigger IRQ on rising edge of Reference A’s LOR.
Trigger IRQ on falling edge of Reference A’s LOR.
Trigger IRQ on rising edge of Reference A’s OOL.
Trigger IRQ on falling edge of Reference A’s OOL.
Description
Reserved.
Trigger IRQ on rising edge of Reference B’s valid.
Trigger IRQ on falling edge of Reference B’s valid.
Trigger IRQ on rising edge of Reference B’s LOR.
Trigger IRQ on falling edge of Reference B’s LOR.
Trigger IRQ on rising edge of Reference B’s OOL.
Trigger IRQ on falling edge of Reference B’s OOL.
Description
Choose either REFA (0) or REFB (1) for use with Bits [4:6].
Select either REFA (0) or REFB (1) LOR signal for output on this pin.
Select either REFA (0) or REFB (1) OOL signal for output on this pin.
Select either REFA (0) or REFB (1). Not Valid signal for output on this pin.
Select phase lock signal for output on this pin.
Select frequency lock signal for output on this pin.
Reserved.
Select IRQ signal for output on this pin.
Rev. D | Page 65 of 76
AD9549