KP125 EVAL BOARD Infineon Technologies, KP125 EVAL BOARD Datasheet - Page 25

• Manufacturer Part Number: KP125 EVAL BOARD
• Description: BOARD EVALUATION KP125
• Manufacturer: Infineon Technologies
• Type: Pressure Sensorr

Specifications of KP125 EVAL BOARD

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: KP125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: KP125EVALBOARDIN

7.1
The address space for SPI communication consists of two main blocks:
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Figure 25
7.2
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The configuration of the serial pins (CLOCK/V
is readable at the data out pin (DATA_OUT). When sending a serial command (regardless if read or write), the
current content of the addressed register can be read out at the DATA_OUT pin after the address has been
recognized. During a read operation only the mode selection bit and the address bits are taken into account
whereas the data bits are ignored. During a write operation, the current content of the addressed register can be
read at DATA_OUT and the content of the data field is written into the register afterwards, provided that the
transmission is complete and correct (frame length, address and enable condition).
User’s Manual
the EEPROM registers (3 bit address)
the control registers (5 bit address)
1 bit write/read (SPI mode: 1 = write/read; 0 = read only)
1 bit mode select (Mode select: 1 = E
3 / 5 bit address (depending on mode)
16 / 10 bit data (depending on mode
SPI address space
SPI Address Space
Data Frames
addr
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
register
EE0
EE1
EE2
EE3
EE4
EE5
EE6
reserved
CSR
TSTCTRL
EEPCTRL
DAC
SGD
GOF
FOF
TOL
TOQ
TGL
TGQ
IIR_LSB
IIR_MSB
LIN_LSB
LIN_MSB
EEPROM Registers
Control Registers
data register, read linearization output bits 11:10
description
EEPROM register, analog trim
EEPROM register, analog trim, memlock
EEPROM register, analog trim
EEPROM register, linearization coefficients
EEPROM register, linearization coefficients / clamping level
EEPROM register, linearization coefficients / clamping level
EEPROM register, column parity
invalid EEPROM register address
configuration register; test mode activation/deactivation, status flags
configuration register, test mode configuration
configuration register, EEPROM control
data register, read/write output DAC
data register, SD-converter gain setting, MAP/BAP mode select
data register, global offset
data register, fine offset
data register, linear offset of temperature compensation
data register, quadratic offset of temperature compensation
data register, linear gain of temperature compensation
data register, quadratic gain of temperature compensation
data register, read/write IIR filter value bits 9:0
data register, read/write IIR filter value bits 11:10
data register, read linearization output bits 9:0
2
PROM register access, 0 = Control register access)
PROG
, DATA_IN, DATA_OUT) is shown in
25
Digital Interface for EEPROM access
Evalkit for Pressure Sensors
Figure
Rev. 1.1, 2007-11-23
1. The response
KP12x Kit