KP125 EVAL BOARD Infineon Technologies, KP125 EVAL BOARD Datasheet - Page 26

• Manufacturer Part Number: KP125 EVAL BOARD
• Description: BOARD EVALUATION KP125
• Manufacturer: Infineon Technologies
• Type: Pressure Sensorr

Specifications of KP125 EVAL BOARD

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: KP125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: KP125EVALBOARDIN

Figure 26
Figure 27
After startup the chip is in normal operation mode and does not react to any read or write command except the
test mode activation sequence on the serial interface. Test mode is enabled by writing a defined sequence into
the status register. Each data frame has a length of either 17 or 21 clock pulses.
The first bit in the transmission frame is the write/read bit. If it is set to 1 a write of the addressed register is
performed.
The second bit is the mode selection bit. This bit determines whether to address EEPROM or command registers,
and defines thereby the length of the SPI frame.
During a read operation additionally only the mode selection bit and the address bits have an influence and data
bits are ignored. The content of the addressed register is shifted to data_out after the address has been
recognized.
During a write operation the addressed register will only be updated after a complete and correct transmission
(frame length, address and enable condition). With the N rising edges of the clock the signal on DATA IN is clocked
into a shift register. The address and the data words are starting with the MSB, respectively. During the falling
edges of the first N-1 clock cycles the DATA IN must be low. The falling edge of the N
write frame. At this time DATA IN must be high. This combination comprises the “enable write frame” signal.
The current content of the addressed register is always written to data_out, regardless from read or write mode.
If an enable condition occurs prior to the 17th/21st clock pulse a read transmission will be interrupted and a write
transmission has no effect; additionally the SPI error flag will be set.
1) Enable condition and Data is ignored for read command.
2) Enable condition and Data is ignored for read command.
User’s Manual
DATA Out
structure
CLOCK/
DATA In
Frame
V
PROG
W/Rn
DATA Out
CLOCK/
DATA In
Mode
structure
Serial Interface Communication Frame for E
Serial Communication Frame for Control Register Access
SPI
V
Frame
PROG
Select
Mode
E
Access
2
PROM
W/Rn
A2
Mode
Register Address
SPI
Select
Mode
A1 A0
Control
Access
A4
D15
A3 A2
D15 D14 D13 D12 D11 D10
Register Address
D14 D13 D12 D11 D10 D9
A1
A0
D9
DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Current Content of Addressed Register
26
D8
Current Content of Addressed Register
2
PROM Register Access
D7
DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1
D6
D8
Data
D7
D5
Data
Digital Interface for EEPROM access
2)
D6
D4
Evalkit for Pressure Sensors
D3
D5
D4
D2
1)
th
D3
D1
clock cycle enables the
Rev. 1.1, 2007-11-23
D2
D0
Enable
D1
KP12x Kit
D0
Enable
DO0