HIP2101IB Intersil, HIP2101IB Datasheet
HIP2101IB
Specifications of HIP2101IB
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HIP2101IB Summary of contents
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... Ordering Information TEMP. PART NUMBER RANGE (°C) PACKAGE HIP2101IB -40 to 125 8 Ld SOIC HIP2101IBZ (Note 1) -40 to 125 8 Ld SOIC (Pb-free) M8.15 HIP2101EIB -40 to 125 8 Ld EPSOIC HIP2101EIBZ -40 to 125 8 Ld EPSOIC (Note 1) ...
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Pinouts HIP2101 (SOIC, EPSOIC) TOP VIEW EPAD NOTE: EPAD = Exposed PAD. Application Block Diagram PWM CONTROLLER 2 HIP2101 HIP2101IR4 (DFN) TOP ...
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Functional Block Diagram *EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best thermal performance connect the EPAD to the PCB power ground plane. +12V PWM +12V PWM FIGURE ...
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Absolute Maximum Ratings Supply Voltage (Notes -0.3V to 18V DD and HI Voltages (Note ...
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Electrical Specifications PARAMETERS BOOT STRAP DIODE Low-Current Forward Voltage High-Current Forward Voltage Dynamic Resistance LO GATE DRIVER Low Level Output Voltage High Level Output Voltage Peak Pullup Current Peak Pulldown Current HO GATE DRIVER Low Level ...
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Pin Descriptions SYMBOL V Positive Supply to lower gate drivers. De-couple this pin High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. HO High-Side ...
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Typical Performance Curves 150° -40° 125° 25°C 0.1 0.01 10 100 FREQUENCY (kHz) FIGURE VSS OPERATING CURRENT vs FREQUENCY 500 ...
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Typical Performance Curves 2.5 2.0 1.5 1 FIGURE 12. PEAK PULLUP CURRENT vs OUTPUT VOLTAGE 1 0.1 0.01 0.001 -4 1•10 -5 1•10 1•10-6 0.3 0.4 0.5 FORWARD ...
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... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for the L dimension TERMINAL TIP MILLIMETERS ...
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... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation ...
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Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α µ 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...