ISL6313 INTERSIL [Intersil Corporation], ISL6313 Datasheet
ISL6313
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ISL6313 Summary of contents
Page 1
... Integrated into the ISL6313 are user programmable current sense resistors, which require only a single external resistor to set their values. No external current sense resistors are required. Another unique feature of the ISL6313 is the addition of a dynamic VID compensation pin that allows optimizing compensation to be added for well controlled dynamic VID response ...
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... Pinout PGOOD VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ISL6313 Integrated Driver Block Diagram PWM SOFT-START AND FAULT LOGIC 2 ISL6313 ISL6313 ISL6313 (36 LD QFN) TOP VIEW GND SHOOT- GATE ...
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... VID4 VID D/A VID3 VID2 VID1 VID0 + + ∑ RGND x2 DVC 2kΩ REF FB COMP OFFSET OFS x1 IOUT OCP V OCP 3 ISL6313 ISL6313 PGOOD SOFT-START AND FAULT LOGIC ADAPTIVE PHASE ALLIGNMENT CIRCUITRY CLOCK AND MODULATOR WAVEFORM GENERATOR OCP ∑ + I_TRIP - + ∑ - E/A FS I_AVG CHANNEL CURRENT BALANCE EN 0 ...
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... Typical Application - ISL6313 FB DVC VSEN COMP APA +5V VCC OFS FS REF SS IOUT ISL6313 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PGOOD EN GND 4 ISL6313 ISL6313 RGND +5V VCC +12V RSET BOOT1 UGATE1 PHASE1 LGATE1 ISEN1- ISEN1+ +12V PVCC BOOT2 UGATE2 PHASE2 LGATE2 ISEN2- ...
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... Typical Application - ISL6313 with NTC Thermal Compensation FB DVC VSEN COMP APA +5V VCC OFS FS REF SS IOUT ISL6313 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PGOOD EN GND 5 ISL6313 ISL6313 RGND +5V VCC RSET +12V BOOT1 UGATE1 PHASE1 LGATE1 ISEN1- ISEN1+ +12V PVCC BOOT2 ...
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... VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature (ISL6313CRZ 0°C to +70°C Ambient Temperature (ISL6313IRZ .-40°C to +85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...
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... IOUT Current Sense Gain R (ISL6313IRZ) 24mV OVERCURRENT PROTECTION Overcurrent Trip Level - Average Normal operation (ISL6313CRZ) Channel Normal operation (ISL6313IRZ) Dynamic VID change Overcurrent Trip Level - Individual Normal operation Channel Dynamic VID change IOUT Pin Overcurrent Trip Level PROTECTION Undervoltage Threshold ...
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... Lower Drive Sink Resistance V OVER TEMPERATURE SHUTDOWN (Note 3) Thermal Shutdown Setpoint Thermal Recovery Setpoint Timing Diagram t PDHUGATE UGATE LGATE t FLGATE 8 ISL6313 ISL6313 TEST CONDITIONS V = 12V, 3nF load, 10% PVCC V = 12V, 3nF load, 10% PVCC V = 12V, 3nF load, 90% PVCC V = 12V, 3nF load, 90% to PVCC ...
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... Connect this pin to the Ground sense pin or point of the microprocessor. 9 ISL6313 ISL6313 FB and COMP These pins are the internal error amplifier inverting input and output respectively. The FB pin, COMP pin, and the VSEN pins are tied together through external R-C networks to compensate the regulator ...
Page 10
... Microprocessor load current profiles have changed to the point that using single-phase regulators is no longer a viable solution. Designing a regulator that is cost-effective, thermally sound, and efficient has become a challenge that only multi-phase converters can accomplish. The ISL6313 10 ISL6313 ISL6313 controller helps simplify implementation by integrating vital functions and requiring minimal external components ...
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... COMP FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION Adaptive Phase Alignment (APA) To further improve the transient response, the ISL6313 also implements Intersil’s proprietary Adaptive Phase Alignment (APA) technique, which turns on all of the channels together at the same time during large current step transient events. ...
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... APA TRIP APA Number of Active Channels The default number of active channels on the ISL6313 is two for 2-phase operation. If single phase operation is desired the ISEN2- pin should be tied to the VCC pin. This will disable Channel 2, so only Channel 1 will fire. In single phase operation all of the Channel 2 pins should be left unconnected including the PHASE2, LGATE2, UGATE2, BOOT2, and ISEN2+ pins ...
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... R ISEN ISEN- Output Voltage Setting ISEN+ The ISL6313 uses a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at RSET the VID pins. The DAC decodes the logic signals into one of VCC the discrete voltages shown in Tables the Intel ...
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... ISL6313 TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VDAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 0 1.57500 1.56875 1.56250 1.55625 ...
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... ISL6313 TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VDAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 0 1.07500 1.06875 1.06250 1.05625 ...
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... ISL6313 TABLE 3. AMD 5-BIT VOLTAGE IDENTIFICATION CODES VDAC VID4 1 0 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 ...
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... DAC) and offset errors in the OFS current source, 1 remote-sense and error amplifiers. Intersil specifies the 0.8250 guaranteed tolerance of the ISL6313 to include the 0 0.8000 combined tolerances of each of these elements. 1 0.7750 The output of the error amplifier ...
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... ISEN Output-Voltage Offset Programming The ISL6313 allows the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R is connected between OFS OFS and VCC, the voltage across it is regulated to 1.6V. This causes a proportional current ( flow into the OFS pin OFS and out of the FB pin, providing a negative offset ...
Page 19
... AC current flowing from the FB to the COMP pin during a VID transition. To create this compensation current the ISL6313 sets the voltage on the DVC pin the voltage on the REF pin. Since the error amplifier forces the voltage on the FB pin and the REF pin to be equal, the resulting voltage across the series RC between DVC and FB is equal to the REF pin voltage ...
Page 20
... Enable and Disable While in shutdown mode, the LGATE and UGATE signals 0.6 0.7 0.8 0.9 1.0 are held low to assure the MOSFETs remain off. The (V) following input conditions must be met, for both Intel and AMD modes of operation, before the ISL6313 is released Q GATE ≥ ------------------------------------- - ΔV BOOT_CAP ⋅ Q PVCC G1 ⋅ ...
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... VBOOT voltage. Then, the controller will regulate the VR voltage at 1.1V for another fixed delay period TD3, of typically 93µs. At the end of TD3 period, ISL6313 will read the VID signals recommended that the VID codes be set no later then 50µs into period TD3. If the VID code is ...
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... FIGURE 14. SOFT-START WAVEFORMS Pre-Biased Soft-Start The ISL6313 also has the ability to start up into a pre-charged output, without causing any unnecessary disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFETs off ...
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... Once an overvoltage condition ends the ISL6313 latches off, and must be reset by toggling EN, or through POR, before a soft-start can be reinitiated. There is an OVP condition that exists that will not latch off the ISL6313 ...
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... FIGURE 17. OVERCURRENT BEHAVIOR IN HICCUP MODE Individual Channel Overcurrent Limiting The ISL6313 has the ability to limit the current in each individual channel without shutting down the entire regulator. This is accomplished by continuously comparing the sensed currents of each channel with a constant 140µA OCL reference current as shown in Figure 16 channel’ ...
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... QFN package is approximately 3.5W at room temperature. See “Layout Considerations” on page 31 for thermal transfer improvement suggestions. When designing the ISL6313 into an application recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs ...
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... EXT1 G1 EXT2 ISL6313 Inductor DCR Current Sensing Component Selection The ISL6313 senses each individual channel’s inductor D current by detecting the voltage across the output inductor C GD DCR of that channel (As described in the “Continuous Current Sensing” on page 12). As Figure 20 illustrates ...
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... Figure 7. This resistor’s FB value sets the desired loadline required for the application. The desired loadline can be calculated by Equation 37 LL where V is the desired droop voltage at the full load DROOP current I FL. 27 ISL6313 . V DROOP R = ------------------------ - LL Based on the desired loadline, the loadline regulation (EQ. 35) resistor ...
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... R FB VSEN FIGURE 22. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6313 CIRCUIT Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately, there is a simple approximation that comes very close to an optimal solution ...
Page 29
... Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). 29 ISL6313 At the beginning of the load transient, the output capacitors , but it can be supply all of the transient current. The output voltage will 0 ...
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... MOSFETs which is related to duty cycle and the number of active phases. For a two-phase design, use Figure 25 to determine the input-capacitor RMS current requirement set by the duty cycle, maximum sustained output current (I of the peak-to-peak inductor current (I 30 ISL6313 0.3 ⎞ (EQ. 46 – ...
Page 31
... Thermal Management For maximum thermal performance in high current, high switching frequency applications, connecting the thermal GND pad of the ISL6313 to the ground plane with multiple vias is recommended. This heat spreading allows the part to achieve its full thermal potential also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part ...
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... VID7 VID6 VID5 VID4 ISL6313 VID3 VID2 VID1 VID0 VRSEL PGOOD EN IOUT R IOUT GND FIGURE 27. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS 32 ISL6313 RGND +5V VCC LOCATE CLOSE SET (MINIMIZE CONNECTION PATH) RSET +12V C BIN1 C BOOT1 BOOT1 UGATE1 PHASE1 LGATE1 ISEN1- ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 33 ISL6313 L36.6x6 A 36 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE ...