ISL6333A INTERSIL [Intersil Corporation], ISL6333A Datasheet
ISL6333A
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ISL6333A Summary of contents
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... Furthermore, the ISL6333 controllers include protection against an open circuit on the remote sensing inputs. Combined, these features provide advanced protection for the microprocessor and power system. 1 ISL6333, ISL6333A, ISL6333B, ISL6333C October 8, 2010 Features • Intel VR11.1 Compatible - IMON Pin for Output Current Monitoring ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Ordering Information PART NUMBER (Note) ISL6333CRZ* ISL6333 CRZ ISL6333IRZ* ISL6333 IRZ ISL6333ACRZ* ISL6333A CRZ ISL6333AIRZ* ISL6333A IRZ ISL6333BCRZ* ISL6333B CRZ ISL6333BIRZ* ISL6333B IRZ ISL6333CCRZ* ISL6333C CRZ ISL6333CIRZ* ISL6333C IRZ *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. ...
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... IDROOP 11 VDIFF 12 RSET 1 OFS VCC 5 6 REF 7 APA 8 COMP DVC CPURST_N 11 VDIFF 12 3 ISL6333A (48 LD QFN) TOP VIEW GND (PIN 49 ISL6333B (48 LD QFN) TOP VIEW ...
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... ISL6333C Same feature set as the ISL6333A controller with two additional changes. The CPURST_N pin is added to eliminate extensive external circuitry required for proper PSI# operation of Intel’s Eaglelake Chipset Platform. The droop pin has been removed and the droop current now flows out of the FB pin. The droop feature is always active. ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Integrated Driver Block Diagram PWM LOW POWER STATE SOFT-START AND FAULT LOGIC 5 LVCC SHOOT- GATE THROUGH CONTROL LOGIC PROTECTION UVCC BOOT UGATE 20kΩ PHASE 10kΩ LGATE FN6520.3 October 8, 2010 ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333 OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC I_AVG OCP I_TRIP APA FS VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 VID1 VID0 1kΩ x2 DVC REF ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333A OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC I_AVG OCP I_TRIP APA FS VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 VID1 VID0 1kΩ x2 DVC REF ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333B OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC I_AVG OCP I_TRIP APA FS VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 VID1 VID0 1kΩ x2 DVC REF ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Block Diagram - ISL6333C OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC I_AVG OCP I_TRIP APA FS VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 VID1 VID0 1kΩ x2 DVC REF ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Typical Application Diagram - ISL6333, ISL6333B VDIFF RGND DVC FB IDROOP COMP APA +5V VCC OFS FS REF ISL6333/B RGND IMON SS VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 CPURST_N PSI# VR_RDY EN GND *NOTE: ISL6333 - Connect the IDROOP pin to the FB pin. The CPURST_N pin does not exist. ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C ISL6333, ISL6333A, ISL6333B, ISL6333C Typical Application Diagram - ISL6333, ISL6333B with NTC Thermal Compensation VDIFF RGND DVC FB IDROOP COMP APA +5V VCC OFS FS REF ISL6333/B RGND IMON SS VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 CPURST_N PSI# VR_RDY EN GND *NOTE: ISL6333 - Connect the IDROOP pin to the FB pin ...
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... VID1 VID0 CPURST_N PSI# VR_RDY EN GND *NOTE: ISL6333A - Connect the IDROOP pin to the FB pin. The CPURST_N pin does not exist. *NOTE: ISL6333C - The CPURST_N pin should connect to the CPURST_N signal. The IDROOP pin does not exist. 12 +5V VCC VSEN RSET PVCC1 ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V Absolute BOOT Voltage GND - 0.3V to GND + 36V BOOT PHASE Voltage GND - 8V (<400ns, 20µJ) to 30V PHASE (<200ns, V UGATE Voltage UGATE PHASE V - 3.5V (<100ns Pulse Width, 2µ PHASE LGATE Voltage, V ...
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... Dynamic VID change IMON Pin Clamped Overcurrent Level OVERVOLTAGE AND UNDERVOLTAGE PROTECTION Undervoltage Threshold VSEN falling Undervoltage Hysteresis VSEN rising 14 ISL6333, ISL6333A, ISL6333B, ISL6333C TEST CONDITIONS = 32.4kΩ from OFS to VCC OFS = 6.04kΩ from OFS to GND OFS = 10k to ground, (Note 100pF, R ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C Electrical Specifications Recommended Operating Conditions. Boldface limits apply over the operating temperature range. (Continued) PARAMETER Overvoltage Threshold During Soft-Start Overvoltage Threshold VR11, VSEN rising Overvoltage Hysteresis VSEN falling SWITCHING TIME (Note 3) UGATE Rise Time t RUGATE; 90% LGATE Rise Time t RLGATE ...
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... This pin is the power supply pin for Channels 2 and 3 lower MOSFET drivers, and should be connected to a +12V supply. Decouple this pin with a quality 1.0µF ceramic capacitor. PVCC1, PVCC2, and PVCC3 (ISL6333A, ISL6333C Only) These pins are the power supply pins for Channels 1, 2, and 3 lower MOSFET drivers, and should be connected to a +12V supply. Decouple these pins with quality 1.0µ ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C RSET Connect this pin to VCC through a resistor to set the effective value of the internal R current sense resistors ISEN recommended a 0.1µF ceramic capacitor be placed in parallel with this resistor for noise immunization. OFS The OFS pin provides a means to program a DC current for generating an offset voltage across the resistor between FB and VSEN ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C . 7A/DIV 7A/DIV L3 PWM3, 5V/DIV PWM2, 5V/DIV I , 7A/DIV L1 PWM1, 5V/DIV 1µs/DIV FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (I combine to form the AC ripple current and the DC load current ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C upper MOSFET and turns on the lower synchronous MOSFET. When the modified V COMP modulator ramp, the PWM output transitions high, turning off the synchronous MOSFET and turning on the upper MOSFET. The PWM signal will remain high until the modified V voltage crosses the modulator ramp again ...
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... CCM mode, and increasing the Channel 1 lower gate drive voltage back to it’s original level. ISL6333A, ISL6333C LOW POWER STATE On the ISL6333A and ISL6333C, when the PSI# pin is set LOW, the controllers change their operating state by turning off all active channels accept for Channel 1. This is the only change made to the regulator ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C Continuous Current Sensing In order to realize proper current-balance, the currents in each channel are sensed continuously every switching cycle. During this time the current-sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current This sensed current scaled version of the inductor current. ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C In Equation 10 the reference voltage, V REF programmed offset voltage the total output current of OUT the converter the internal sense resistor connected ISEN to the ISEN+ pin the feedback resistor the active FB number of channels, and DCR is the Inductor DCR value. ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C Compensating Dynamic VID Transitions During a VID transition, the resulting change in voltage on the FB pin and the COMP pin causes an AC current to flow through the error amplifier compensation components from the FB to the COMP pin. This current then flows through the feedback ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C . EXTERNAL CIRCUIT ISL6333, ISL6333B INTERNAL CIRCUIT PVCC1 +12V GVOT 1.0µF REG. BYP1 LVCC1 1.0µ F PVCC2_3 LVCC2, LVCC3 +12V 1.0µF UVCC1, UVCC2, PUVCC UVCC3 +5V TO +12V LVCC = LOWER GATE DRIVE 1.0µ F UVCC = UPPER GATE DRIVE FIGURE 12. INTERNAL GATE DRIVE CONNECTIONS AND ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C Upper MOSFET Gate Drive Voltage Versatility The controllers provide the user flexibility in choosing the upper MOSFET gate drive voltage for efficiency optimization. The controllers tie all the upper gate drive rails together to the PUVCC pin. Simply applying a voltage from + +12V on PUVCC sets all of the upper gate drive rail voltages simultaneously ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C ramp times, t and t , can be calculated based Equations 20 and 21: 3 – ⋅ ⋅ ⋅ ( μ 1 – 3 ⋅ ⋅ ⋅ ( μ – 1 VID SS For example, when VID is set to 1.5V and the R 100kΩ, the first soft-start ramp time t ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C pulls the output voltage below a level that might cause damage to the load. The LGATE outputs remain high until VDIFF falls 110mV below the OVP threshold that tripped the overvoltage protection circuitry. The controllers will continue to protect the load in this fashion as long as the overvoltage condition recurs ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C OUTPUT CURRENT, 50A/DIV 0A OUTPUT VOLTAGE, 500mV/DIV 0V FIGURE 19. OVERCURRENT BEHAVIOR IN HICCUP MODE Individual Channel Overcurrent Limiting The controllers have the ability to limit the current in each individual channel without shutting down the entire regulator. This is accomplished by continuously comparing the sensed currents of each channel with a constant 140µ ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance, P ...
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... FIGURE 23. TIME CONSTANT MISMATCH BEHAVIOR Loadline Regulation Resistor If load line regulation is desired on the ISL6333 and ISL6333A, the IDROOP pin should be connected to the FB pin in order for the internal average sense current to flow out across the loadline regulation resistor, labeled R Figure 7. The ISL6333B and ISL6333C always have the load line regulation enabled ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C In Equation 40 the per-channel filter inductance divided by the number of active channels the sum total of all output capacitors; ESR is the equivalent series resistance of the bulk output filter capacitance; and V peak-to-peak sawtooth signal amplitude, as described in the “Electrical Specifications” on page 13. ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. The output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C enough to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. For a three-phase design, use Figure 27 to determine the input-capacitor RMS current requirement set by the duty cycle, maximum sustained output current (I of the peak-to-peak inductor current (I 0 ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C DVC DVC DVC VDIFF VSEN IDROOP COMP R APA APA +5V VCC (CF1) R OFS OFS FS REF ISL6333 REF VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI# VR_RDY EN IMON R IMON GND FIGURE 30 ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C The power components should be placed first, which includes the MOSFETs, input and output capacitors, and the inductors important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. Symmetrical layout allows heat to be dissipated equally across all power trains ...
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... ISL6333, ISL6333A, ISL6333B, ISL6333C Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 4/10 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 40 4X 5.5 A 44X 0. 48X 0 . 40± BOTTOM VIEW ± SIDE VIEW ( 44X 0 ...