ISL6540A Intersil Corporation, ISL6540A Datasheet
ISL6540A
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ISL6540A Summary of contents
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... LGATE ISL6540ACRZA ISL6540ACRZ 5x5 QFN L28.5x5 PVCC 16 ISL6540AIRZ ISL6540AIRZA ISL6540AIRZ - 5x5 QFN L28.5x5 LINDRV 15 *Add “-T” suffix for tape and reel. 14 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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... Block Diagram 2 ISL6540A FN6288.2 March 12, 2007 ...
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... OFS- SS LINDRV ISL6540A BOOT BOOT VCC PVCC BOOT R HSOC HSOC C HSOC UGATE PHASE LGATE PGND R LSOC LSOC ISL6540A C LSOC COMP VMON VSEN+ VSEN- GND GND C HFIN C BIN C BOOT Q1 L OUT C HFOUT C BOUT Q2 10Ω ...
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... ISL6540A BOOT BOOT F1 VCC PVCC BOOT R HSOC HSOC C HSOC UGATE PHASE LGATE PGND R LSOC LSOC ISL6540A C LSOC COMP VMON VCC VSEN+ VSEN- GND GND C HFIN C BIN C BOOT Q1 L OUT C BOUT C Q2 ...
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... OFS- OFS ISL6540A BOOT VCC PVCC BOOT R HSOC HSOC C HSOC UGATE PHASE LGATE PGND R LSOC LSOC ISL6540A C LSOC COMP VMON VSEN+ VSEN- LINDRV GND GND C HFIN C BIN C BOOT Q1 L OUT C HFOUT ...
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... VFF_R POR Falling VFF Threshold VFF_F POR VFF Hysterisis VFF_H 6 ISL6540A Thermal Information Thermal Resistance (Note 1, 2) QFN Package (Note Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150° -0. (DC) Maximum Lead Temperature (Soldering 10s +300° ...
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... VSEN- Input Common Mode Range Max Input Common Mode Range Min V VSEN- Disable Voltage VSEN_DIS INTERNAL LINEAR REGULATOR I Maximum Current VIN 7 ISL6540A TEST CONDITIONS GBD GBD FS = 250kHz to 2MHz, VFF = 3.3V to 20V VCC = 5V Leading and Trailing-edge Modulation Leading and Trailing-edge Modulation VCC = 5V REFIN = 0. 1μ ...
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... OVF T PGOOD Delay PG_DLY I PGOOD Delay Source Current PG_DLY PGOOD Delay Threshold Voltage V PG_DLY 8 ISL6540A TEST CONDITIONS VIN = 22V, Load = 0 to 100mA VIN = 12V step, PVCC = 0 V VIN = 5 12V step, PVCC = 5 0.1μ Pin 0.1μ Pin SS 500mA Source Current, PVCC = 5 ...
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... OFS+ and OFS- pins translates to a -200mV offset of the system reference. VCC (Pin 8, Analog Circuit Bias) This pin provides power for the ISL6540A analog circuitry. The pin should be connected to a 2.9V to 5.5V bias through an RC filter from PVCC to prevent noise injection into the analog circuitry ...
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... PGND. A 100 across R developed across the low side MOSFET when on. The sinking current limit is set the nominal sourcing limit in ISL6540A. An initial ~120ns blanking period is used to eliminate the sampling error due to switching noise before the current is measured. μ F capacitor ...
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... Functional Description Initialization The ISL6540A automatically initializes upon receipt of power without requiring any special sequencing of the input supplies. The Power-On Reset (POR) function continually HIGH = ABOVE POR; LOW = BELOW POR VCC POR VFF POR AND PVCC POR EN POR FIGURE 1. SOFT-START INITIALIZATION LOGIC monitors the input supply voltages (PVCC, VFF, VCC) and the voltage at the EN pin ...
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... The ISL6540A monitors both the high side MOSFET and low side MOSFET for overcurrent events. Dual sensing allows the ISL6540A to detect overcurrent faults at the very low and very high duty cycles that can result from the ISL6540A’s wide input range. The OCP function is enabled with the drivers at startup and detects the peak current during each sensing period ...
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... See the ISL6605 datasheet for specification parameters that are not defined in the current ISL6540A electrical specifications table. A 1-2Ω resistor is recommended series with the bootstrap diode when using VCCs above 5.0V to prevent the bootstrap capacitor from overcharging due to the negative swing of the trailing edge of the phase node ...
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... OFS increased. In both modes the voltage difference between OFS+ and OFS- is then sensed with an instrumentation amplifier and is converted to the desired margining voltage by a 5:1 ratio. The maximum designed margining range of the ISL6540A is ±200mV, this sets the MINIMUM value approximately 5.9K ...
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... Figure 8 should be located as close together as possible. Please note that the capacitors C and C O Locate the ISL6540A within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6540A must be sized to handle peak current. ...
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... As the ISL6540A supports 100% duty cycle, d and 180°. 0dB uses feedforward compensation, as such Figures 9 and 10. Use the following guidelines for ...
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... Figure 11 shows an asymptotic plot of the DC/DC converter’s gain vs. frequency. The actual modulator gain has a high gain 17 ISL6540A peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop ...
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... Given a sufficiently fast control loop design, the ISL6540A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 ISL6540A MOSFET Selection/Considerations The ISL6540A requires 2 N-Channel power MOSFETs. These should be selected based upon r 0.5Io requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors ...
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... CORNER REF. OPTION 4X BOTTOM VIEW SECTION "C-C" TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE 20 ISL6540A L28.5x5 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE SYMBOL 0. ...