PESD5V0L6US,118 NXP Semiconductors, PESD5V0L6US,118 Datasheet - Page 8

• Manufacturer Part Number: PESD5V0L6US,118
• Description: DIODE 6FOLD ESD PROTECT 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: TVSr
• Series: -r

Specifications of PESD5V0L6US,118

• Package / Case: 8-SOIC (3.9mm Width)
• Voltage - Reverse Standoff (typ): 5V
• Voltage - Breakdown: 6.8V
• Power (watts): 35W
• Polarization: 6 Channel Array - Bidirectional
• Mounting Type: Surface Mount
• Polarity: Unidirectional
• Clamping Voltage: 15 V
• Operating Voltage: 5 V
• Breakdown Voltage: 6.4 V
• Peak Surge Current: 2.5 A
• Peak Pulse Power Dissipation: 35 W
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 65 C
• Dimensions: 4(Max) mm W x 5(Max) mm L
• Number Of Elements: 6
• Package Type: SO
• Operating Temperature Classification: Military
• Reverse Breakdown Voltage: 6.4V
• Reverse Stand-off Voltage: 5V
• Leakage Current (max): 25nA
• Peak Pulse Current: 2.5A
• Test Current (it): 1mA
• Operating Temp Range: -65C to 150C
• Mounting: Surface Mount
• Pin Count: 8
• Capacitance Value: 19 pF
• Maximum Clamping Voltage: 15 V
• Direction Type: Uni-Directional
• Number Of Elements Per Chip: 6
• Esd Protection Voltage: 10@HBM|20@Contact Disc KV
• Maximum Leakage Current: 0.025 uA
• Maximum Working Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4520-2; 934057934118; PESD5V0L6US /T3; PESD5V0L6US /T3

NXP Semiconductors
7. Application information
PESD5V0L6UAS_US_3
Product data sheet
The PESD5V0L6UAS and the PESD5V0L6US are designed for protection of up to six
unidirectional data lines from the damage caused by ElectroStatic Discharge (ESD) and
surge pulses. The PESD5V0L6UAS and the PESD5V0L6US may be used on lines where
the signal polarity is above or below ground.
The PESD5V0L6UAS and the PESD5V0L6US provide a surge capability of 35 W per line
for a 8/20 s waveform.
Circuit board layout and protection device placement:
Circuit board layout is critical for the suppression of ESD, EFT and surge transients. The
following guidelines are recommended:
1. Place the protection device as close to the input terminal or connector as possible.
2. The path length between the protection device and the protected line should be
3. Keep parallel signal paths to a minimum.
4. Avoid running protection conductors in parallel with unprotected conductor.
5. Minimize all printed-circuit board conductive loops including power and ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer printed-circuit
Fig 8.
minimized.
boards, use ground vias.
Typical application for ESD protection of data lines
unidirectional protection of 6 lines
PESD5V0L6UAS
PESD5V0L6US
PESD5V0L6UAS; PESD5V0L6US
Rev. 03 — 18 August 2009
Low capacitance 6-fold ESD protection diode arrays
bidirectional protection of 5 lines
PESD5V0L6UAS
PESD5V0L6US
n.c.
n.c.
© NXP B.V. 2009. All rights reserved.
006aaa065
high speed
data lines
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