DSPIC30F3012-30I/P Microchip Technology, DSPIC30F3012-30I/P Datasheet - Page 25

• Manufacturer Part Number: DSPIC30F3012-30I/P
• Description: IC DSPIC MCU/DSP 24K 18DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/P

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 12
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F3012-30IP

2.4.1
The 17 x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17 x 17-bit
multiplier/scaler
sign-extended to 40 bits. Integer data is inherently
represented as a signed two’s complement value,
where the MSB is defined as a sign bit. Generally
speaking, the range of an N-bit two’s complement
integer is -2
range is -32768 (0x8000) to 32767 (0x7FFF) including
‘0’. For a 32-bit integer, the data range is
-2,147,483,648
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a two’s
complement fraction, where the MSB is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit two’s
complement fraction with this implied radix point is -1.0
to (1 – 2
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including ‘0’
and has a precision of 3.01518x10
mode, the 16x16 multiply operation generates a 1.31
product, which has a precision of 4.65661 x 10
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiplies.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands direct a 16-bit
result. Word operands direct a 32-bit result to the
specified register(s) in the W array.
2.4.2
The
adder/subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
through the barrel shifter prior to accumulation.
© 2010 Microchip Technology Inc.
data
1-N
). For a 16-bit fraction, the Q15 data range
N-1
MULTIPLIER
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
accumulator
to 2
(0x8000 0000)
is
N-1
source
– 1. For a 16-bit integer, the data
a
33-bit
consists
and
to
value
post-accumulation
-5
dsPIC30F2011/2012/3012/3013
. In Fractional
2,147,483,645
of
which
a
-10
40-bit
.
is
2.4.2.1
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtracter
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS register:
• Overflow from bit 39: This is a catastrophic
• Overflow into guard bits 32 through 39: This is a
The adder has an additional saturation block which
controls accumulator data saturation if selected. It uses
the result of the adder, the overflow Status bits
described above, and the mode control bits SATA/B
(CORCON<7:6>) and ACCSAT (CORCON<4>)
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow. They are:
• OA: ACCA overflowed into guard bits
• OB: ACCB overflowed into guard bits
• SA: ACCA saturated (bit 31 overflow and
• SB: ACCB saturated (bit 31 overflow and
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic
corresponding overflow trap flag enable bit (OVATE,
OVBTE) in the INTCON1 register (refer to
“Interrupts”) is set. This allows the user to take
immediate action, for example, to correct system gain.
overflow in which the sign of the accumulator is
destroyed.
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
warning
Adder/Subtracter, Overflow and
Saturation
trap
when
DS70139G-page 25
set
Section 8.0
and
the
to