DSPIC30F3012-30I/P Microchip Technology, DSPIC30F3012-30I/P Datasheet - Page 59

IC DSPIC MCU/DSP 24K 18DIP

DSPIC30F3012-30I/P

Manufacturer Part Number
DSPIC30F3012-30I/P
Description
IC DSPIC MCU/DSP 24K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/P

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
12
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F3012-30IP

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7.0
All of the device pins (except V
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
7.1
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
All port pins have three registers directly associated
with the operation of the port pin. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
FIGURE 7-1:
© 2010 Microchip Technology Inc.
Note:
I/O PORTS
Parallel I/O (PIO) Ports
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Data Bus
WR TRIS
WR LAT +
WR Port
Read LAT
Read Port
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Read TRIS
Peripheral Module
DD
PIO Module
, V
TRIS Latch
dsPIC30F2011/2012/3012/3013
Data Latch
SS
D
D
CK
CK
, MCLR and
Q
Q
Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins and writes to the
port pins, write the latch (LATx).
Any bit and its associated data and Control registers
that are not valid for a particular device are disabled.
That means the corresponding LATx and TRISx
registers and the port pin read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
A parallel I/O (PIO) port that shares a pin with a
peripheral is, in general, subservient to the peripheral.
The peripheral’s output buffer data and control signals
are provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell.
shared with other peripherals and the associated I/O
cell (pad) to which they are connected.
The format of the registers for the shared ports,
(PORTB, PORTC, PORTD and PORTF) are shown in
Table 7-1
Note:
1
0
1
0
Output Enable
Output Data
Output Multiplexers
through
The actual bits in use vary between
devices.
Input Data
I/O Cell
Figure 7-1
Table
I/O Pad
7-6.
illustrates how ports are
DS70139G-page 59

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