PIC24HJ64GP506-I/PT Microchip Technology, PIC24HJ64GP506-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC24HJ64GP506-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP506-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: 3-Wire/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 13
• Operating Supply Voltage: 0 V to 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 18-ch x 12-bit
• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 8KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• Embedded Interface Type: CAN, I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24HJXXXGPX06/X08/X10
TABLE 1:
TABLE 2:
DS80444D-page 2
PIC24HJ256GP206
PIC24HJ256GP210
PIC24HJ256GP610
Note 1:
Note 1:
Compare
Module
Output
ECAN
ECAN
ECAN
Mode
I
Doze
ADC
ADC
CPU
CPU
ADC
2
SPI
SPI
SPI
C™
2:
The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on
Device and Revision IDs for your specific device.
Only those issues indicated in the last column apply to the current silicon revision.
Part Number
Transmission
Transmission
Master Mode
Bus Collision
Slave Select
12-bit Mode
10-bit Mode
Sleep Mode
PWM Mode
Instruction
Instruction
Loopback
Sampling
Feature
SILICON DEVREV VALUES (CONTINUED)
SILICON ISSUE SUMMARY
Frame
Mode
EXCH
DISI
Data
Data
—
Number
Item
10.
12.
13.
14.
11.
3.
1.
2.
4.
5.
6.
7.
8.
9.
When Doze mode is enabled, any writes to a peripheral SFR
can cause other updates to that register to cease to function
for the duration of the current CPU clock cycle.
For this revision of silicon, the 12-bit ADC module INL, DNL
and signal acquisition time parameters are not within the
published data sheet specifications.
For this revision of silicon, the 10-bit ADC module DNL,
conversion speed, and signal acquisition time parameters are
not within the published data sheet specifications.
The EXCH instruction does not execute correctly.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
The output compare module will miss one compare event
when the duty cycle register value is updated from 0x0000 to
0x0001.
The SPI module will fail to generate frame synchronization
pulses in Frame Master mode.
The SPI module slave select functionality will not work
correctly.
The SMP bit does not have any effect when the SPI module is
configured for a 1:1 prescale factor in Master mode.
ECAN transmissions may be incorrect if any buffers other than
Buffer 0 are enabled as transmit buffers.
Under specific conditions, the first five bits of a transmitted
identifier may not match the value in the transmit buffer ID
register.
The ECAN module (ECAN1 or ECAN2) does not function
correctly in Loopback mode.
The Bus Collision Status bit does not get set when a bus
collision occurs during a Restart or Stop event.
ADC event triggers from the INT0 pin will not wake-up the
device from Sleep or Idle mode if the SMPI bits are non-zero.
Device ID
0x007B
0x0071
0x0073
(1)
Issue Summary
Revision ID for Silicon Revision
0x3002
A2
© 2010 Microchip Technology Inc.
0x3004
A3
Revisions
A2 A3 A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
0x3040
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
X
(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)