PIC24FJ128GA110-I/PT Microchip Technology, PIC24FJ128GA110-I/PT Datasheet - Page 160

• Manufacturer Part Number: PIC24FJ128GA110-I/PT
• Description: IC PIC MCU FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA110-I/PT

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCU
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ256GA110 FAMILY
REGISTER 13-1:
DS39905B-page 158
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-10
bit 9-8
bit 7
bit 6-5
bit 4
bit 3
bit 2-0
Note 1:
ENFLT0
R/W-0
U-0
—
2:
The OCx output must also be configured to an available RPn pin. For more information, see Section 9.4
“Peripheral Pin Select”.
OCFA pin controls OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and OCxRS are
double-buffered only in PWM modes.
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare x in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
OCTSEL2:OCTSEL0: Output Compare x Timer Select bits
111 = System Clock
110 = Reserved
101 = Reserved
100 = Timer1
011 = Timer5
010 = Timer4
001 = Timer3
000 = Timer2
Unimplemented: Read as ‘0’
ENFLT0: Fault 0 Input Enable bit
1 = Fault 0 input is enabled
0 = Fault 0 input is disabled
Unimplemented: Read as ‘0’
OCFLT0: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is only cleared by software
OCM2:OCM0: Output Compare x Mode Select bits
111 = Center-Aligned PWM Mode on OCx
110 = Edge-Aligned PWM Mode on OCx
101 = Double Compare Continuous Pulse mode: Initialize OCx pin low, toggle OCx state continuously
100 = Double Compare Single-Shot mode: Initialize OCx pin low, toggle OCx state on matches of OCxR
011 = Single Compare Continuous Pulse mode: Compare events continuously toggle OCx pin
010 = Single Compare Single-Shot mode: Initialize OCx pin high, compare event forces OCx pin low
001 = Single Compare Single-Shot mode: Initialize OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
U-0
U-0
—
—
on alternate matches of OCxR and OCxRS
and OCxRS for one cycle
OCxCON1: OUTPUT COMPARE x CONTROL 1 REGISTER
HCS = Hardware Clearable/Settable bit
W = Writable bit
‘1’ = Bit is set
OCSIDL
R/W-0
U-0
—
R/W-0, HCS
OCTSEL2
OCFLT0
R/W-0
Preliminary
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRIGMODE
OCTSEL1
R/W-0
R/W-0
(1)
OCTSEL0
OCM2
R/W-0
R/W-0
(1)
© 2008 Microchip Technology Inc.
x = Bit is unknown
OCM1
R/W-0
U-0
—
(1)
OCM0
R/W-0
U-0
—
(1)
bit 8
bit 0