PIC24FJ128GA110-I/PT Microchip Technology, PIC24FJ128GA110-I/PT Datasheet - Page 50
![IC PIC MCU FLASH 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC24FJ128GA110-I/PT
Manufacturer Part Number
PIC24FJ128GA110-I/PT
Description
IC PIC MCU FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA106-IPT.pdf
(14 pages)
2.PIC24FJ128GA106-IPT.pdf
(330 pages)
3.PIC24FJ128GA106-IPT.pdf
(52 pages)
4.PIC24FJ128GB110-IPF.pdf
(292 pages)
Specifications of PIC24FJ128GA110-I/PT
Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC24
No. Of I/o's
85
Ram Memory Size
16KB
Cpu Speed
32MHz
No. Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCU
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ128GA110-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC24FJ128GA110-I/PT
Manufacturer:
MICROCHIP
Quantity:
8 000
- PIC24FJ128GA106-IPT PDF datasheet
- PIC24FJ128GA106-IPT PDF datasheet #2
- PIC24FJ128GA106-IPT PDF datasheet #3
- PIC24FJ128GB110-IPF PDF datasheet #4
- Current page: 50 of 292
- Download datasheet (6Mb)
PIC24FJ256GA110 FAMILY
3.3.3
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This provides transparent access of stored constant
data from the data space without the need to use
special instructions (i.e., TBLRDL/H).
Program space access through the data space occurs if
the Most Significant bit of the data space EA is ‘1’, and
program space visibility is enabled by setting the PSV bit
in the CPU Control register (CORCON<2>). The loca-
tion of the program memory space to be mapped into the
data space is determined by the Program Space Visibil-
ity Page Address register (PSVPAG). This 8-bit register
defines any one of 256 possible pages of 16K words in
program space. In effect, PSVPAG functions as the
upper 8 bits of the program memory address, with the
15 bits of the EA functioning as the lower bits. Note that
by incrementing the PC by 2 for each program memory
word, the lower 15 bits of data space addresses directly
map to the lower 15 bits in the corresponding program
space addresses.
Data reads to this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 3-7), only the lower 16 bits of the
FIGURE 3-7:
DS39905B-page 48
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space....
When CORCON<2> =
PSVPAG
02
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
PROGRAM SPACE VISIBILITY OPERATION
23
1
Program Space
and EA<15> =
15
1
:
0
018000h
000000h
010000h
800000h
Preliminary
24-bit program word are used to contain the data. The
upper 8 bits of any program space locations used as
data should be programmed with ‘1111
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions will
require one instruction cycle in addition to the specified
execution time. All other instructions will require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
• Execution upon re-entering the loop after an
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
Note:
interrupt
interrupt is serviced
Data Space
PSV Area
PSV access is temporarily disabled during
table reads/writes.
0000h
8000h
FFFFh
© 2008 Microchip Technology Inc.
...while the lower 15
bits of the EA specify
an exact address
within the PSV area.
This corresponds
exactly to the same
lower 15 bits of the
actual program space
address.
Data EA<14:0>
1111’ or
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