PIC24FJ128GA110-I/PT Microchip Technology, PIC24FJ128GA110-I/PT Datasheet - Page 225

• Manufacturer Part Number: PIC24FJ128GA110-I/PT
• Description: IC PIC MCU FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA110-I/PT

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCU
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

21.0
The triple comparator module provides three dual-input
comparators. The inputs to the comparator can be con-
figured to use any one of four external analog inputs as
well, as a voltage reference input from either the
internal band gap reference divided by two (V
the comparator voltage reference generator.
FIGURE 21-1:
© 2008 Microchip Technology Inc.
Note:
CCH1:CCH0
CREF
C
C
C
V
C
CV
BG
X
X
X
X
INB
INC
IND
INA
REF
TRIPLE COMPARATOR
MODULE
/2
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
Select
Logic
Input
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
-
+
-
+
-
+
C1
C2
C3
BG
PIC24FJ256GA110 FAMILY
/2) or
Preliminary
EVPOL1:EVPOL0
EVPOL1:EVPOL0
CPOL
EVPOL1:EVPOL0
CPOL
CPOL
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module in shown in
Figure 21-1. Diagrams of the possible individual com-
parator configurations are shown in Figure 21-2.
Each comparator has its own control register,
CMxCON (Register 21-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 21-2).
Trigger/Interrupt
Trigger/Interrupt
Trigger/Interrupt
Logic
Logic
Logic
COE
COE
COE
CEVT
CEVT
COUT
COUT
CEVT
COUT
DS39905B-page 223
C1OUT
C2OUT
C3OUT
Pin
Pin
Pin