PIC24FJ128GA110-I/PT Microchip Technology, PIC24FJ128GA110-I/PT Datasheet - Page 60

• Manufacturer Part Number: PIC24FJ128GA110-I/PT
• Description: IC PIC MCU FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA110-I/PT

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCU
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ256GA110 FAMILY
TABLE 5-3:
DS39905B-page 58
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
Reset Type
2:
3:
4:
5:
6:
T
T
regulator is disabled.
T
T
oscillator clock to the system.
T
T
STARTUP
OST
POR
RST
LOCK
FSCM
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
= Internal state Reset time (32 μs nominal).
= Power-on Reset delay (10 μs nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
EC, FRC, FRCDIV, LPRC T
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC, FRC, FRCDIV, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
Any Clock
Any clock
Any Clock
Any Clock
Any Clock
= PLL lock time.
= Fail-Safe Clock Monitor delay (100 μs nominal).
= T
Clock Source
VREG
(10 μs nominal) if on-chip regulator is enabled or T
T
T
T
POR
POR
POR
POR
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
Preliminary
+ T
+ T
+ T
+ T
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
RST
RST
RST
RST
+ T
+ T
+ T
+ T
RST
RST
RST
RST
System Clock
T
T
OST
OST
T
T
Delay
T
T
LOCK
LOCK
+ T
+ T
OST
OST
—
—
—
—
—
—
—
—
LOCK
LOCK
PWRT
(64 ms nominal) if on-chip
© 2008 Microchip Technology Inc.
FSCM
T
T
T
T
T
T
Delay
FSCM
FSCM
FSCM
FSCM
FSCM
FSCM
—
—
—
—
—
—
—
—
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
2, 3
2, 3, 5, 6
2, 3, 4, 6
2, 3, 4, 5, 6
3
3
3
3
3
3
Notes