AT89C51ED2-SLSUM Atmel, AT89C51ED2-SLSUM Datasheet - Page 80
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AT89C51ED2-SLSUM
Manufacturer Part Number
AT89C51ED2-SLSUM
Description
IC 8051 MCU FLASH 64K 44PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.ATWEBDVK-02RC.pdf
(137 pages)
Specifications of AT89C51ED2-SLSUM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Package
44PLCC
Device Core
8051
Family Name
89C
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
34
Interface Type
SPI/UART
Number Of Timers
3
Processor Series
AT89x
Core
8051
Data Ram Size
2 KB
Maximum Clock Frequency
40 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Cpu Family
AT89
Device Core Size
8b
Frequency (max)
40MHz
Total Internal Ram Size
2KB
# I/os (max)
34
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51ED2-SLSUM
Manufacturer:
MITSUBISHI
Quantity:
43
Part Number:
AT89C51ED2-SLSUM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
18. Power Management
18.1
18.2
18.2.1
18.2.2
80
Introduction
Idle Mode
AT89C51RD2/ED2
Entering Idle Mode
Exiting Idle Mode
Two power reduction modes are implemented in the AT89C51RD2/ED2. The Idle mode and the
Power-Down mode. These modes are detailed in the following sections. In addition to these
power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2
using the X2 mode detailed in Section “Enhanced Features”, page 17.
Idle mode is a power reduction mode that reduces the power consumption. In this mode, pro-
gram execution halts. Idle mode freezes the clock to the CPU at known states while the
peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e.,
the program counter and program status word register retain their data for the duration of Idle
mode. The contents of the
Idle mode is detailed in Table 18-1.
To enter Idle mode, set the IDL bit in PCON register (see Table 18-2). The AT89C51RD2/ED2
enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL
bit is the last instruction executed.
Note:
There are two ways to exit Idle mode:
Note:
1. Generate an enabled interrupt.
2. Generate a reset.
– Hardware clears IDL bit in PCON register which restores the clock to the CPU.
– A logic high on the RST pin clears IDL bit in PCON register directly and
Execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Idle mode. The general purpose
flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt
occurred during normal operation or during Idle mode. When Idle mode is exited by
an interrupt, the interrupt service routine may examine GF1 and GF0.
asynchronously. This restores the clock to the CPU. Program execution momentarily
resumes with the instruction immediately following the instruction that activated the
Idle mode and may continue for a number of clock cycles before the internal reset
algorithm takes control. Reset initializes the AT89C51RD2/ED2 and vectors the CPU
to address C:0000h.
If IDL bit and PD bit are set simultaneously, the AT89C51RD2/ED2 enters Power-Down mode.
Then it does not go in Idle mode when exiting Power-Down mode.
During the time that execution resumes, the internal RAM cannot be accessed; however, it is pos-
sible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction
immediately following the instruction that activated Idle mode should not write to a Port pin or to
the external RAM.
SFRs
and RAM are also retained. The status of the Port pins during
4235K–8051–05/08