AT89C51ED2-SLSUM Atmel, AT89C51ED2-SLSUM Datasheet - Page 94
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AT89C51ED2-SLSUM
Manufacturer Part Number
AT89C51ED2-SLSUM
Description
IC 8051 MCU FLASH 64K 44PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.ATWEBDVK-02RC.pdf
(137 pages)
Specifications of AT89C51ED2-SLSUM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Package
44PLCC
Device Core
8051
Family Name
89C
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
34
Interface Type
SPI/UART
Number Of Timers
3
Processor Series
AT89x
Core
8051
Data Ram Size
2 KB
Maximum Clock Frequency
40 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Cpu Family
AT89
Device Core Size
8b
Frequency (max)
40MHz
Total Internal Ram Size
2KB
# I/os (max)
34
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51ED2-SLSUM
Manufacturer:
MITSUBISHI
Quantity:
43
Part Number:
AT89C51ED2-SLSUM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
24.3
24.3.1
24.3.2
94
Flash Registers and Memory Map
AT89C51RD2/ED2
Hardware Register
Flash Memory Lock Bits
The AT89C51RD2/ED2 Flash memory uses several registers for its management:
The only hardware register of the AT89C51RD2/ED2 is called Hardware Byte or Hardware
Security Byte (HSB).
Table 24-1.
Boot Loader Jump Bit (BLJB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
By default, this bit is programmed and the ISP is enabled.
The three lock bits provide different levels of protection for the on-chip code and data when pro-
grammed as shown in Table 24-2.
• Hardware register can only be accessed through the parallel programming modes which are
• Software registers are in a special page of the Flash memory which can be accessed through
• When this bit is programmed (‘0’ value) the boot address is F800h.
• When this bit is unprogrammed (‘1’ value) the boot address is 0000h.
Number
handled by the parallel programmer.
the API or with the parallel programming modes. This page, called "Extra Flash Memory", is
not in the internal Flash program memory addressing space.
2-0
Bit
7
6
5
4
3
X2
7
Mnemonic
XRAM
LB2-0
BLJB
Hardware Security Byte (HSB)
Bit
BLJB
X2
-
-
6
Description
X2 Mode
Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.
Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset (Default).
Boot Loader Jump Bit
Unprogrammed (‘1’ value) to start the user’s application on next reset at address 0000h.
Programmed (‘0’ value) to start the boot loader at address F800h on next reset (Default).
Reserved
Reserved
XRAM config bit (only programmable by programmer tools)
Programmed to inhibit XRAM.
Unprogrammed, this bit to valid XRAM (Default).
User Memory Lock Bits (only programmable by programmer tools)
See Table 24-2
5
-
4
-
XRAM
3
LB2
2
LB1
1
4235K–8051–05/08
LB0
0