LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 15

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
3.5.2 Peripheral reset control register
3.5.3 System PLL control register
Table 6.
This register allows software to reset the SSP and I2C peripherals. Writing a 0 to the
SSP_RST_N or I2C_RST_N bits resets the SSP or I2C peripheral. Writing a 1 de-asserts
the reset.
Remark: Before accessing the SSP and I2C peripherals, write a 1 to this register to
ensure that the reset signals to the SSP and I2C are de-asserted.
Table 7.
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock used by the CPU, peripherals, and optionally the USB
subsystem. Note that the USB subsystem has its own dedicated PLL. The PLL can
produce a clock up to the maximum allowed for the CPU, which is 72 MHz.
Bit
1:0
31:2
Bit
0
1
31:2
Symbol
MAP
-
Symbol
SSP_RST_N
I2C_RST_N
-
System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit
description
Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
All information provided in this document is subject to legal disclaimers.
Value
00
01
10 or
11
-
Value
0
1
0
1
-
Rev. 2 — 7 July 2010
Description
System memory remap
Boot Loader Mode. Interrupt vectors are re-mapped to Boot
ROM.
User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
Reserved
Description
SSP reset control
SSP reset enabled
SSP reset de-asserted
I2C reset control
I2C reset enabled
I2C reset de-asserted
Reserved
Chapter 3: LPC13xx System configuration
UM10375
© NXP B.V. 2010. All rights reserved.
16 of 333
Reset
value
0
0
0x00
Reset
value
10
0x00