LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 30

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
3.5.32 POR captured PIO status register 0
3.5.33 POR captured PIO status register 1
3.5.34 BOD control register
The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1,
and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of
one GPIO pin. This register is a read-only status register.
Table 37.
The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2
(PIO2_8 to PIO2_11) and port 3 at power-on-reset. Each bit represents the reset state of
one PIO pin. This register is a read-only status register.
Table 38.
The BOD control register selects four separate threshold values for sending a BOD
interrupt to the NVIC. Only one level is allowed for forced reset.
Table 39.
Bit
11:0
23:12
31:24
Bit
0
1
2
3
4
5
6
7
8
9
31:10
Bit
1:0
Symbol
CAPPIO0_11 to
CAPPIO0_0
CAPPIO1_11 to
CAPPIO1_0
CAPPIO2_7 to
CAPPIO2_0
Symbol
CAPPIO2_8
CAPPIO2_9
CAPPIO2_10
CAPPIO2_11
CAPPIO3_0
CAPPIO3_1
CAPPIO3_2
CAPPIO3_3
CAPPIO3_4
CAPPIO3_5
-
Symbol
BODRSTLEV
POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit
description
POR captured PIO status registers 1 (PIOPORCAP1, address 0x4004 8104) bit
description
BOD control register (BODCTRL, address 0x4004 8150) bit description
All information provided in this document is subject to legal disclaimers.
Value
00
01 -11 Reserved
Description
Raw reset status input PIO0_11 to
PIO0_0
Raw reset status input PIO1_11 to
PIO1_0
Raw reset status input PIO2_7 to
PIO2_0
Description
Raw reset status input PIO2_8
Raw reset status input PIO2_9
Raw reset status input PIO2_10
Raw reset status input PIO2_11
Raw reset status input PIO3_0
Raw reset status input PIO3_1
Raw reset status input PIO3_2
Raw reset status input PIO3_3
Raw reset status input PIO3_4
Raw reset status input PIO3_5
Reserved
Rev. 2 — 7 July 2010
Description
BOD reset level
The reset assertion threshold voltage is 1.49 V; the
reset de-assertion threshold voltage is 1.64 V.
Chapter 3: LPC13xx System configuration
Reset value
User implementation dependent
User implementation dependent
User implementation dependent
Reset value
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
-
User implementation dependent
User implementation dependent
User implementation dependent
UM10375
© NXP B.V. 2010. All rights reserved.
31 of 333
Reset
value
0x00