LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 67

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
5.6.12 Interrupt Priority Register 1
5.6.11 Interrupt Priority Register 0
The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 73.
The IPR1 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 74.
Bit
2:0
7:3
10:8
15:11 IP_PIO0_1
18:16 Unimplemented
23:19 IP_PIO0_2
26:24 Unimplemented
31:27 IP_PIO0_3
Bit
2:0
7:3
10:8
15:11 IP_PIO0_5
18:16 Unimplemented
23:19 IP_PIO0_6
26:24 Unimplemented
31:27 IP_PIO0_7
Unimplemented
Unimplemented
Name
IP_PIO0_0
Unimplemented
Name
IP_PIO0_4
Unimplemented
Interrupt Priority Register 0 (IPR0 - address 0xE000 E400) bit description
Interrupt Priority Register 1 (IPR1 - address 0xE000 E404) bit description
All information provided in this document is subject to legal disclaimers.
Description
These bits ignore writes, and read as 0.
PIO0_0 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
PIO0_1 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
PIO0_2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
PIO0_3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Description
These bits ignore writes, and read as 0.
PIO0_4 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
PIO0_5 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
PIO0_6 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
PIO0_7 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Rev. 2 — 7 July 2010
Chapter 5: LPC13xx Interrupt controller
UM10375
© NXP B.V. 2010. All rights reserved.
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