P87C54SBAA,512 NXP Semiconductors, P87C54SBAA,512 Datasheet - Page 20

• Manufacturer Part Number: P87C54SBAA,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C54SBAA,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1252-5; 935258650512; P87C54SBAA

Philips Semiconductors
2000 Aug 07
NOTE:
*SMOD0 is located at PCON6.
**f
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
OSC
Tl
Symbol
FE
SM0
SM1
SM2
REN
TB8
RB8
Rl
= oscillator frequency
Bit Addressable
Bit:
Function
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
0
0
1
1
SCON Address = 98H
(SMOD0 = 0/1)*
SM0/FE
7
SM1
0
1
0
1
SM1
Mode
6
0
1
2
3
Figure 7. SCON: Serial Port Control Register
SM2
5
Description
shift register
8-bit UART
9-bit UART
9-bit UART
REN
4
Baud Rate**
f
variable
f
variable
OSC
OSC
20
TB8
/12
/64 or f
3
OSC
RB8
/32
2
8XC51RA+/RB+/RC+/RD+/80C51RA+
Tl
1
Rl
0
8XC51FA/FB/FC/80C51FA
Reset Value = 0000 0000B
Product specification
8XC54/58
SU00043