LPC2210FBD144/01,5 NXP Semiconductors, LPC2210FBD144/01,5 Datasheet - Page 38

• Manufacturer Part Number: LPC2210FBD144/01,5
• Description: IC ARM7 MCU 16KRAM W/ADC 144LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2200r

Specifications of LPC2210FBD144/01,5

• Program Memory Type: ROMless
• Package / Case: 144-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC22
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/SSP/UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM10091 - KIT DEV PHYCORE-ARM7/LPC2220622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K568-1757 - BOARD EVAL FOR LPC220X ARM MCU
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4012; 935282078551; LPC2210FBD144/01-S

NXP Semiconductors
Table 14.
C
LPC2210_2220_6
Product data sheet
Symbol
Common to read and write cycles
t
t
t
t
Read cycle parameters
t
t
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
t
t
t
t
t
CHAV
CHCSL
CHCSH
CHANV
CSLAV
OELAV
CSLOEL
am
am(ibr)
am(sbr)
h(D)
CSHOEH
OEHANV
CHOEL
CHOEH
AVCSL
CSLDV
CSLWEL
CSLBLSL
WELDV
CSLDV
WELWEH
BLSLBLSH
WEHANV
WEHDNV
BLSHANV
L
= 25 pF; T
External memory interface dynamic characteristics
Parameter
XCLK HIGH to address valid
time
XCLK HIGH to CS LOW time
XCLK HIGH to CS HIGH
time
XCLK HIGH to address
invalid time
CS LOW to address valid
time
OE LOW to address valid
time
CS LOW to OE LOW time
memory access time
memory access time (initial
burst-ROM)
memory access time
(subsequent burst-ROM)
data hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
XCLK HIGH to OE LOW time
XCLK HIGH to OE HIGH
time
address valid to CS LOW
time
CS LOW to data valid time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
BLS LOW to BLS HIGH time
WE HIGH to address invalid
time
WE HIGH to data invalid time
BLS HIGH to address invalid
time
amb
= 40 C.
Conditions
Rev. 06 — 11 December 2008
[2][3]
[2][3]
[2][5]
[2][4]
[2][4]
[1]
[1]
[4]
[4]
[6]
[1]
[2]
[2]
[2]
Min
-
-
-
-
(T
( 20)
(T
( 20)
T
0
T
T
T
T
(2
T
5
5
5
5
5
5
5
5
5
5
5
5
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
T
cy(CCLK)
+ ( 20)
10
(1 + WST2)
(1 + WST2)
5
5
(2 + WST1)) +
(2 + WST1)) +
)
5
16/32-bit ARM microcontrollers
5
5
LPC2210/2220
Typ Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
10
10
10
+10
+10
+5
-
-
-
-
+5
+5
+5
+5
-
+5
+5
+5
+5
+5
T
(1 + WST2) + 5
T
(1 + WST2) + 5
T
(2
T
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
T
© NXP B.V. 2008. All rights reserved.
cy(CCLK)
+ 5
+ 5
) + 5 ns
38 of 50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns