LPC2129FBD64/01,15 NXP Semiconductors, LPC2129FBD64/01,15 Datasheet - Page 21

• Manufacturer Part Number: LPC2129FBD64/01,15
• Description: IC ARM7 MCU FLASH 256K 64-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2129FBD64/01,15

• Program Memory Type: FLASH
• Program Memory Size: 256KB (256K x 8)
• Package / Case: 64-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 46
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC21
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/JTAG/SPI/SSP/UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC2129, KSK-LPC2129-PL, KSK-LPC2129E, KSK-LPC2129E-PL
• Development Tools By Supplier: OM10041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Package: 64LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 60 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100MCB2100 - BOARD EVAL NXP LPC211X/LPC212X622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4315; 935284889151; LPC2129FBD64/01-S; LPC2129FBD64/01-S

NXP Semiconductors
Product data sheet
LPC2109_2119_2129_6
6.18.2 PLL
6.18.3 Reset and wake-up timer
6.18.4 Code security (Code Read Protection - CRP)
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and
bypassed following a chip Reset and may be enabled by software. The program must
configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a
clock source. The PLL settling time is 100 s.
Reset has two sources on the LPC2109/2119/2129: the RESET pin and Watchdog Reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip Reset by any source starts the Wake-up Timer (see Wake-up Timer description
below), causing the internal chip reset to remain asserted until the external Reset is
de-asserted, the oscillator is running, a fixed number of clocks have passed, and the
on-chip flash controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is the Reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of Reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
This feature of the LPC2109/2119/2129 allows the user to enable different levels of
security in the system so that access to the on-chip flash and use of the JTAG and ISP
can be restricted. When needed, CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
Rev. 06 — 10 December 2007
DD
ramp (in the case of power on), the type of crystal
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
© NXP B.V. 2007. All rights reserved.
21 of 44