ADUC834BSZ Analog Devices Inc, ADUC834BSZ Datasheet - Page 54

• Manufacturer Part Number: ADUC834BSZ
• Description: IC ADC DUAL16/24BIT W/MCU 52MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC834BSZ

• Core Size: 8-Bit
• Program Memory Size: 62KB (62K x 8)
• Oscillator Type: Internal
• Core Processor: 8052
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 3x16b, 4x24b; D/A 1x12b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Controller Family/series: (8052) ADUC
• No. Of I/o's: 26
• Eeprom Memory Size: 62KB
• Ram Memory Size: 2KB
• Cpu Speed: 12.58MHz
• Package: 52MQFP
• Device Core: 8052
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Interface Type: I2C/SPI/UART
• On-chip Adc: 4-chx16-bit|4-chx24-bit
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC834
TIMER/COUNTER 0 AND 1 OPERATING MODES
The following paragraphs describe the operating modes for
Timer/Counters 0 and 1. Unless otherwise noted, it should be
assumed that these modes of operation are the same for Timer 0
as for Timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter with a divide-by-32
prescaler. Figure 48 shows Mode 0 operation.
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer over-
flow flag. The overflow flag, TF0, can then be used to request
an interrupt. The counted input is enabled to the timer when
TR0 = 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows
the timer to be controlled by external input INT0, to facilitate
pulsewidth measurements. TR0 is a control bit in the special
function register TCON; Gate is in TMOD. The 13-bit register
consists of all eight bits of TH0 and the lower five bits of TL0.
The upper three bits of TL0 are indeterminate and should be
ignored. Setting the run flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. Mode 1 is shown in Figure 49.
*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL")
P3.4/T0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL")
P3.4/T0
P3.2/INT0
P3.2/INT0
CORE
CORE
CLK*
CLK*
GATE
GATE
Figure 48. Timer/Counter 0, Mode 0
Figure 49. Timer/Counter 0, Mode 1
12
12
TR0
TR0
C/ T = 0
C/ T = 1
C/ T = 0
C/ T = 1
CONTROL
CONTROL
(5 BITS)
(8 BITS)
TL0
TL0
(8 BITS)
(8 BITS)
TH0
TH0
TF0
TF0
INTERRUPT
INTERRUPT
–54–
Mode 2 (8-Bit Timer/Counter with Auto Reload)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload, as shown in Figure 50. Overflow from
TL0 not only sets TF0, but also reloads TL0 with the contents
of TH0, which are preset by software. The reload leaves TH0
unchanged.
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 51.
TL0 uses the timer 0 control bits: C/T, Gate, TR0, INT0, and
TF0. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer 1.
Thus, TH0 now controls the “Timer 1” interrupt. Mode 3 is
provided for applications requiring an extra 8-bit timer or counter.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off
by switching it out of and into its own Mode 3, or can still be
used by the serial interface as a baud rate generator. In fact, it
can be used, in any application not requiring an interrupt from
Timer 1 itself.
*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL")
P3.4/T0
P3.2/INT0
P3.2/INT0
P3.4/T0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL")
CORE
CLK*
CLK/12
GATE
CORE
CLK*
CORE
GATE
TR1
Figure 50. Timer/Counter 0, Mode 2
Figure 51. Timer/Counter 0, Mode 3
12
12
TR0
TR0
C/ T = 0
C/ T = 1
C/ T = 0
C/ T = 1
CORE
CLK/12
CONTROL
CONTROL
RELOAD
(8 BITS)
(8 BITS)
(8 BITS)
(8 BITS)
TH0
TL0
TH0
TL0
TF0
TF0
TF1
INTERRUPT
REV. A
INTERRUPT
INTERRUPT