ADUC834BSZ Analog Devices Inc, ADUC834BSZ Datasheet
ADUC834BSZ
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ADUC834BSZ Summary of contents
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FEATURES High Resolution - ADCs 2 Independent ADCs (16-Bit and 24-Bit Resolution) 24-Bit No Missing Codes, Primary ADC 21-Bit rms (18.5-Bit p-p) Effective Resolution @ 20 Hz Offset Drift 10 nV/ C, Gain Drift 0.5 ppm/ C Memory 62 ...
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ADuC834 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SPECIFICATIONS 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications T Parameter ADC SPECIFICATIONS Conversion Rate Primary ADC 2 No Missing Codes Resolution Output Noise ...
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ADuC834 SPECIFICATIONS (continued) Parameter INTERNAL REFERENCE ADC Reference Reference Voltage Power Supply Rejection Reference Tempco DAC Reference Reference Voltage Power Supply Rejection Reference Tempco ANALOG INPUTS/REFERENCE INPUTS Primary ADC Differential Input Voltage Ranges Bipolar Mode (ADC0CON3 = 0) 2 Analog ...
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Parameter TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current AIN– Current Initial Tolerance @ 25°C Drift EXCITATION CURRENT SOURCES Output Current Initial Tolerance @ 25°C Drift Initial Current Matching @ 25°C Drift Matching Line Regulation ( Load Regulation 2 Output ...
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ADuC834 SPECIFICATIONS (continued) Parameter LOGIC OUTPUTS (Not Including XTAL2 Output High Voltage Output Low Voltage OL 2 Floating State Leakage Current Floating State Output Capacitance POWER SUPPLY MONITOR (PSM) AV Trip Point Selection Range ...
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Parameter POWER REQUIREMENTS Power Supply Voltages Nominal Operation Nominal Operation Nominal Operation Nominal Operation POWER CONSUMPTION Power Supply ...
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ADuC834 NOTES 1 Temperature Range for ADuC834BS (MQFP package) is –40°C to +125°C. Temperature Range for ADuC834BCP (CSP package) is –40°C to +85°C. 2 These numbers are not production tested but are guaranteed by design and/or characterization data on production ...
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ABSOLUTE MAXIMUM RATINGS (T = 25°C, unless otherwise noted AGND . . . . . . . . . . . . . . . . . . . . . . . –0 ...
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ADuC834 AIN1 BUF AIN AIN2 MUX AIN3 AUXILIARY ADC AIN AIN4 MUX AIN5 TEMP BAND GAP SENSOR REFERENCE REFIN V REF DETECT REFIN 200 A 200 A IEXC 1 CURRENT SOURCE MUX IEXC ...
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Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 3–4, 2–3, P1.2–P1.7 9–12 11–14 P1.2/DAC/IEXC1 I/O P1.3/AIN5/IEXC2 I/O P1.4/AIN1 P1.5/AIN2 P1.6/AIN3 P1.7/AIN4/DAC AGND 7 9 REFIN(– REFIN(+) SS 13 ...
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ADuC834 Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 28–31 30–33 P2.0–P2.7 36–39 39–42 (A8–A15) (A16–A23 XTAL1 33 35 XTAL2 PSEN ALE 43–46 46–49 P0.0–P0.7 49–52 52–55 (AD0–AD3) (AD4–AD7) *I ...
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MEMORY ORGANIZATION The ADuC834 contains four different memory blocks, namely: • 62 Kbytes of On-Chip Flash/EE Program Memory • 4 Kbytes of On-Chip Flash/EE Data Memory • 256 bytes of General-Purpose RAM • 2 Kbytes of Internal XRAM (1) Flash/EE ...
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ADuC834 When accessing the internal XRAM, the P0 and P2 port pins, as well as the RD and WR strobes, will not be output as per a standard 8051 MOVX instruction. This allows the user to use these port pins ...
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Stack Pointer (SP and SPH) The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the ‘top of the stack.’ The SP Register is incremented before data is stored during PUSH ...
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ADuC834 COMPLETE SFR MAP Figure 6 shows a full SFR memory map and the SFR contents after RESET. NOT USED indicates unoccupied SFR loca- tions. Unoccupied locations in the SFR address space are not ISPI WCOL SPE SPIM CPOL CPHA ...
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ADC SFR INTERFACE Both ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following pages. ADCSTAT ADC Status Register. Holds general status of the primary and auxiliary ADCs. ...
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ADuC834 ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable No Bit Name Description 7 ––– Reserved for Future Use 6 ––– Reserved for Future Use 5 ...
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ADC0CON (Primary ADC Control Register) and ADC1CON (Auxiliary ADC Control Register) The ADC0CON and ADC1CON SFRs are used to configure the primary and auxiliary ADC for reference and channel selection, unipolar or bipolar coding and, in the case of the ...
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ADuC834 ADC0H/ADC0M/ADC0L (Primary ADC Conversion Result Registers) These three 8-bit registers hold the 24-bit conversion result from the primary ADC. SFR Address ADC0H ADC0M ADC0L Power-On Default Value 00H Bit Addressable No ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers) These two ...
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SF (Sinc Filter Register) The number in this register sets the decimation factor and thus the output update rate for the primary and auxiliary ADCs. This SFR cannot be written by user software while either ADC is active. The update ...
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ADuC834 PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE Tables X, XI, and XII show the output rms noise in V and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update rates on both the ...
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PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview The ADuC834 incorporates two independent - ADCs (primary and auxiliary) with on-chip digital filtering intended for the measure- ment of wide dynamic range, low frequency signals such as those in weigh-scale, strain gage, ...
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ADuC834 Auxiliary ADC The auxiliary ADC is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. This ADC is not buffered and has a fixed input range 2.5 V (assuming ...
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Primary and Auxiliary ADC Inputs The output of the primary ADC multiplexer feeds into a high impedance input stage of the buffer amplifier result, the pri- mary ADC inputs can handle significant source impedances and are tailored for ...
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ADuC834 Reference Input The ADuC834’s reference inputs, REFIN(+) and REFIN(–), provide a differential reference input capability. The common- mode range for these differential inputs is from AGND to AV The nominal reference voltage, V (REFIN(+) – REFIN(–)), REF for specified ...
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In operation, the analog signal sample is fed to the difference amplifier along with the output of the feedback DAC. The difference between these two signals is integrated and fed to the comparator. The output of the comparator provides the ...
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ADuC834 ADC Chopping Both ADCs on the ADuC834 implement a chopping scheme whereby the ADC repeatedly reverses its inputs. The decimated digital output words from the Sinc3 filters therefore have a positive offset and negative offset term included ...
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Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory. EPROM TECHNOLOGY ...
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ADuC834 Flash/EE Program Memory The ADuC834 contains a 64 Kbyte array of Flash/EE program memory. The lower 62 Kbytes of this program memory is avail- able to the user, and can be used for program storage or indeed as additional ...
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Alternatively ULOAD Mode can be used to save data to the 56 Kbytes of Flash/EE memory. This can be extremely useful in datalogging applications where the ADuC834 can provide Kbytes of NV data memory on-chip (4 Kbytes ...
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ADuC834 Using the Flash/EE Data Memory The 4 Kbytes of Flash/EE data memory is configured as 1024 pages, each of 4 bytes. As with the other ADuC834 peripherals, the interface to this memory space is via a group of registers ...
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Programming the Flash/EE Data Memory A user wishes to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other three bytes already in this page. A typical program of the Flash/EE ...
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ADuC834 DAC The ADuC834 incorporates a 12-bit, voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. It has two selectable ranges nal bandgap 2.5 V reference) and 0 ...
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Note that Figure 22 represents a transfer function in 0-to-V mode only. In 0-to-V mode (with V REF nonlinearity would be similar, but the upper portion of the transfer function would follow the “ideal” line right to the end, showing ...
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ADuC834 PULSEWIDTH MODULATOR (PWM) The PWM on the ADuC834 is a highly flexible PWM offering programmable resolution and input clock, and can be config- ured for any one of six different modes of operation. Two of these modes allow the ...
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PWM MODES OF OPERATION Mode 0: PWM Disabled The PWM is disabled, allowing P1.0 and P1.1 be used as normal. Mode 1: Single-Variable Resolution PWM In Mode 1, both the pulse length and the cycle time (period) are programmable in ...
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ADuC834 Mode 4: Dual NRZ 16-Bit - DAC Mode 4 provides a high speed PWM output similar to that of a Σ-∆ DAC. Typically, this mode will be used with the PWM clock equal to 12.58 MHz. In this mode, ...
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ON-CHIP PLL The ADuC834 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can oper- ate at this ...
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ADuC834 TIME INTERVAL COUNTER (WAKE-UP/RTC TIMER) A time interval counter (TIC) is provided on-chip for: • periodically waking the part up from power-down • implementing a Real-Time Clock • counting longer intervals than the standard 8051 compatible timers are capable ...
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INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set ...
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ADuC834 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC834 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. ...
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POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies ( the ADuC834. It will DD DD indicate when any of the supply pins drop below one of four user-selectable ...
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ADuC834 SERIAL PERIPHERAL INTERFACE The ADuC834 integrates a complete hardware Serial Peripheral Interface (SPI) interface on-chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. It ...
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SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. SFR Address F7H Power-On Default Value ...
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ADuC834 SERIAL INTERFACE The ADuC834 supports a fully licensed interface is implemented as a full hardware slave and software master. SDATA (Pin 27) is the data I/O pin and SCLOCK (Pin 26) is ...
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The main features of the MicroConverter I • Only two bus lines are required; a serial data line (SDATA) and a serial clock line (SCLOCK). 2 • master can communicate with multiple slave devices. Because each slave ...
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ADuC834 DUAL DATA POINTER The ADuC834 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON also includes features such as automatic hardware post-increment and post-decrement, ...
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COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. These remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via ...
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ADuC834 P1.2 to P1.7 The remaining Port 1 pins (P1.2–P1.7) can only be configured as analog input (ADC) or digital input pins. By (power-on) default, these pins are configured as analog inputs, i.e., ‘1’ written in the corresponding Port 1 ...
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Notice also that direct access to the SCLOCK and SDATA/MOSI pins is afforded through the SFR interface in I Therefore, if you are not using the SPI or I use these two pins to give additional high current digital outputs. ...
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ADuC834 TIMERS/COUNTERS The ADuC834 has three 16-bit Timer/Counters: Timer 0, Timer 1, and Timer 2. The Timer/Counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in soft- ware. Each Timer/Counter ...
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TCON Timer/Counter 0 and 1 Control Register SFR Address 88H Power-On Default Value 00H Bit Addressable Yes Bit Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the Program ...
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ADuC834 TIMER/COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer ...
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TIMER/COUNTER 2 OPERATING MODES The following paragraphs describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XXIX. Table XXVIII. Timer 2 Operating Modes RCLK (or) TCLK CAP2 ...
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ADuC834 T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 will not be set when either ...
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UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive ...
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ADuC834 Mode 1: 8-Bit UART, Variable Baud Rate Mode 1 is selected by clearing SM0 and setting SM1. Each data byte (LSB first) is preceded by a start bit (0) and followed by a stop bit (1). Therefore 10 bits ...
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BAUD RATE GENERATION USING TIMER 1 AND TIMER 2 Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate ...
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ADuC834 BAUD RATE GENERATION USING TIMER 3 The high integer dividers in a UART block means that high speed baud rates are not always possible using some particular crystals. e.g., using a 12 MHz crystal, a baud rate of 115200 ...
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INTERRUPT SYSTEM The ADuC834 provides a total of 11 interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs. These are the IE (Interrupt Enable) Register, the IP (Interrupt ...
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ADuC834 Interrupt Priority The Interrupt Enable registers are written by the user to enable individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each inter- rupt. An interrupt of a ...
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ADuC834 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design consider- ations that must be addressed when integrating the ADuC834 into any hardware system. External Memory Interface In addition to its internal program and data memories, the ...
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ADuC834 Power Supplies The ADuC834’s operational power supply voltage range is 2 5.25 V. Although the guaranteed data sheet specifica- tions are given only for power supplies within 2 3 the nominal ...
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Power Saving Modes Setting the Idle and Power-Down Mode Bits, PCON.0 and PCON.1 respectively, in the PCON SFR described in Table II allows the chip to be switched from Normal mode into Idle mode, and also into full Power-Down mode. ...
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ADuC834 PLACE ANALOG a. COMPONENTS HERE AGND PLACE ANALOG b. COMPONENTS HERE AGND PLACE ANALOG c. COMPONENTS HERE GND Figure 64. System Grounding Schemes If the user plans to connect fast logic signals (rise/fall time < 5 ns) to any ...
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OTHER HARDWARE CONSIDERATIONS In-Circuit Serial Download Access Nearly all ADuC834 designs will want to take advantage of the in-circuit reprogrammability of the chip. This is accomplished by a connection to the ADuC834’s UART, which requires an external RS-232 chip for ...
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ADuC834 Typical System Configuration A typical ADuC834 configuration is shown in Figure 66. It summarizes some of the hardware considerations discussed in the previous paragraphs. Figure 66 also includes connections for a typical analog measure- ment application of the ADuC834, ...
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QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC834. The system consists of the following PC-based (Windows hardware and software development tools. Hardware: ADuC834 Evaluation Board, and Serial Port Cable ...
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ADuC834 TIMING SPECIFICATIONS Parameter CLOCK INPUT (External Clock Driven XTAL1) t XTAL1 Period CK t XTAL1 Width Low CKL t XTAL1 Width High CKH t XTAL1 Rise Time CKR t XTAL1 Fall Time CKF 1/t ADuC834 Core ...
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Parameter EXTERNAL PROGRAM MEMORY t ALE Pulsewidth LHLL t Address Valid to ALE Low AVLL t Address Hold after ALE Low LLAX t ALE Low to Valid Instruction In LLIV ALE Low to PSEN Low t LLPL PSEN Pulsewidth t ...
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ADuC834 Parameter EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth t RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX RD Low to Valid Data In t RLDV Data and Address Hold after RD t ...
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Parameter EXTERNAL DATA MEMORY WRITE CYCLE WR Pulsewidth t WLWH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX ALE Low to WR Low t LLWL Address Valid to WR Low t AVWL Data Valid ...
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ADuC834 Parameter UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold after ...
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Parameter SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time ...
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ADuC834 Parameter SPI MASTER MODE TIMING (CPHA = 0) t SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge DAV t Data Output Setup before SCLOCK Edge DOSU t Data Input Setup Time ...
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Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge ...
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ADuC834 Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK ...
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Parameter 2 I C-SERIAL INTERFACE TIMING t SCLOCK Low Pulsewidth L t SCLOCK High Pulsewidth H t Start Condition Hold Time SHD t Data Setup Time DSU t Data Hold Time DHD t Setup Time for Repeated Start RSU t ...
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ADuC834 1.03 0.88 0.73 SEATING PLANE VIEW A PIN 1 INDICATOR 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE Revision History Location 4/03—Data Sheet changed from REV REV. A. Updated OUTLINE DIMENSIONS . . . . . ...