ADUC836 Analog Devices, ADUC836 Datasheet

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... On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. The ADuC836 is supported by a QuickStart™ development system featuring low cost software and hardware development tools. One Technology Way, P .O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...

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... Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 ADC Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . . .29 Flash/EE Memory and the ADuC836 . . . . . . . . . . . . . . . . .29 ADuC836 Flash/EE Memory Reliability . . . . . . . . . . . . . . .29 Flash/EE Program Memory . . . . . . . . . . . . . . . . . . . . . . . .30 Serial Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Parallel Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 User Download Mode (ULOAD .31 Flash/EE Program Memory Security . . . . . . . . . . . . . . . . . .31 Lock, Secure, and Serial Safe Modes . . . . . . . . . . . . . . . . . .31 Using the Flash/EE Data Memory ...

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... Hz Update Rate 13.5 Range = ±20 mV Update Rate 16 Range = ±2. Update Rate See Tables X and XI in Output Noise Varies with Selected ADuC836 ADC Description Update Rate and Gain Range ±15 1 LSB ±3 ±10 ±10 Range = ± ±640 mV ±0.5 Range = ±1. ±2.56 V ± ...

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... ANALOG (DAC) OUTPUT Voltage Range Resistive Load Capacitive Load Output Impedance I SINK TEMPERATURE SENSOR Accuracy Thermal Impedance ( ADuC836 Test Conditions/Comments 1.25 ± 1% Initial Tolerance @ 25° 100 2.5 ± 1% Initial Tolerance @ 25° ±100 External Reference Voltage = 2.5 V RN2, RN1, RN0 of ADC0CON Set to ± ...

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... –5– ADuC836 Unit nA typ nA typ % typ %/°C typ A typ % typ ppm/°C typ % typ ppm/°C typ A/V typ A/V typ V max V min V max V max V min V min/V max V min/V max ...

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... Wake-Up with SPI Interrupt Wake-Up with TIC Interrupt Wake-Up with External RESET Oscillator Powered Down Wake-Up with INT0 Interrupt Wake-Up with SPI Interrupt Wake-Up with External RESET FLASH/EE MEMORY RELIABILITY CHARACTERISTICS 16 Endurance 17 Data Retention ADuC836 Test Conditions/Comments 0.4 ...

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... Osc Osc. Off = 125°C; Osc Osc. Off = 2 3 5.25 V, Core CLK = 1.57 MHz = 85°C; Osc. On, TIC On = 125°C; Osc. On, TIC 85°C; MAX = 5. 125°C; MAX ADuC836 Unit V min V max V min V max V min V max V min V max mA max mA typ mA max  ...

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... ADuC836 NOTES 1 Temperature range for ADuC836BS (MQFP package) is –40°C to +125°C. Temperature range for ADuC836BCP (CSP package) is –40°C to +85°C. 2 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 3 System Zero-Scale Calibration can remove this error. ...

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... CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC836 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges.Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... IEXC 1 CURRENT SOURCE MUX IEXC *PIN NUMBERS REFER TO THE 52-LEAD MQFP PACKAGE SHADED AREAS REPRESENT THE NEW FEATURES OF THE ADuC836 OVER THE ADuC816 Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 1, 2 56, 1 P1.0/P1.1 P1.0/T2/PWM0 P1.1/T2EX/PWM1 I/O 3–4, 2–3, P1.2– ...

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... I Input to the Crystal Oscillator Inverter O Output from the Crystal Oscillator Inverter. (See the Hardware Design Considerations section for description.) –11– ADuC836 SPI Interface input, this pin is a ...

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... ADuC836 Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic PSEN 42 45 ALE 43–46 46–49 P0.0–P0.7 49–52 52–55 (AD0–AD3 Input Output Supply. PIN FUNCTION DESCRIPTIONS (continued) Type* Description I/O External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000h to F7FFh ...

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... Figure 2. Lower 128 Bytes of Internal Data Memory (4) Internal XRAM The ADuC836 contains 2 Kbytes of on-chip extended data mem- ory. This memory, although on-chip, is accessed via the MOVX instruction. The 2 Kbytes of internal XRAM are mapped into the bottom 2 Kbytes of the external address space if the CFG836.0 bit is set ...

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... MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. The ADuC836, however, can access Mbytes of external data memory. This is an enhancement of the 64 Kbytes external data memory space available on a standard 8051 compatible core. ...

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... Table II. The TIC (Wake-Up/RTC timer) can be used to accurately wake up the ADuC836 from power-down at regular intervals. To use the TIC to wake up the ADuC836 from power-down, the OSC_PD bit in the PLLCON SFR must be clear and the TIC must be enabled. ...

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... ADuC836 COMPLETE SFR MAP Figure 6 shows a full SFR memory map and the SFR con- tents after RESET. NOT USED indicates unoccupied SFR locations. Unoccupied locations in the SFR address space are ISPI WCOL SPE SPIM CPOL CPHA FFH 0 FEH 0 FDH 0 FCH 0 FBH ...

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... GN0M/H GN1L/H Table IV. ADCSTAT SFR Bit Designations . REF –17– ADuC836 Primary ADC 16-bit conversion result is held in these two 8-bit registers. Auxiliary ADC 16-bit conversion result is held in these two 8-bit registers. Primary ADC 16-bit Offset Calibration Coefficient is held in these two 8-bit registers. ...

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... ADuC836 ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable No Bit Name Description 7 ––– Reserved for Future Use 6 ––– Reserved for Future Use 5 ADC0EN Primary ADC Enable. ...

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... V–2. Unipolar Mode) Table VII. ADC1CON SFR Bit Designations Positive Input Negative Input AIN3 AGND AIN4 AGND Temp Sensor AGND (Temp Sensor routed to the ADC input) AIN5 AGND –19– ADuC836 ). REF Auxiliary ADC Control SFR D3H 00H No = 1.25 V). REF = 2.5 V) REF ...

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... ADuC836 ADC0H/ADC0M (Primary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the primary ADC. SFR Address ADC0H ADC0M Power-On Default Value 00H Bit Addressable No ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC. ...

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... SF Register will MOD be that programmed by user software. SF(dec and con- ADC 255 Table IX. ICON SFR Bit Designations –21– ADuC836 . As mentioned earlier, all calibra- ADC Table VIII. SF SFR Bit Designations SF(hex) f (Hz) ADC 0D 105 ...

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... ADuC836 PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE Tables X, XI, and XII show the output rms noise in mV and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update rates on both the primary and auxiliary ADCs. The numbers are typical and are generated at a differential input voltage of 0 V.The output update rate is selected Table X. Primary ADC, Typical Output RMS Noise ( ...

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... PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview The ADuC836 incorporates two independent - ADCs (primary and auxiliary) with on-chip digital filtering intended for the mea- surement of wide dynamic range, low frequency signals such as those in weigh-scale, strain gage, pressure transducer, or tempera- ture measurement applications ...

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... ADC. When the analog input channel is switched, the settling time of the part must elapse before a new valid word is available from the ADC. DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC836 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION. THE EXTERNAL - ADC REFERENCE VOLTAGE IS SELECTED VIA THE XREF1 BIT IN ADC1CON. THE  ...

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... For example, if AIN(–) is 2.5 V and the primary ADC is configured for an analog input range mV, the input voltage range on the AIN(+) input AIN(–) is 2.5 V and the ADuC836 is configured for an analog input range of 1.28 V, the analog input range on the AIN(+) input is 1. 3.78 V (i.e., 2.5 V ± 1.28 V). ...

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... REFIN(+) and REFIN(–) pins goes below 0 either the REFIN(+) or REFIN(–) inputs is open circuit, the ADuC836 detects that it no longer has a valid reference. In this case, the NOXREF bit of the ADCSTAT SFR is set the ADuC836 is performing normal conversions and the NOXREF bit becomes active, the conversion results revert to all 1s ...

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... In this manner, the 1-bit output of the comparator is translated into a band-limited, low noise output from the ADuC836 ADCs. The ADuC836 filter is a low-pass, SIN primary function is to remove the quantization noise introduced at the modulator ...

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... The ADuC836 provides four calibration modes that can be pro- grammed via the mode bits in the ADCMODE SFR detailed in Table V. In fact, every ADuC836 has already been factory cali- brated. The resultant Offset and Gain calibration coefficients for both the primary and auxiliary ADCs are stored on-chip in manufacturing-specific Flash/EE memory locations ...

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... REV. A ADuC836 Flash/EE Memory Reliability The Flash/EE program and data memory arrays on the ADuC836 are fully qualified for two key Flash/EE memory characteristics: Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention. ...

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... ADuC836 Flash/EE Program Memory The ADuC836 contains a 64 Kbyte array of Flash/EE program memory. The lower 62 Kbytes of this program memory are avail- able to the user, and can be used for program storage or indeed as additional NV data memory. The upper 2 Kbytes of this Flash/EE program memory array con- tain permanently embedded firmware, allowing in-circuit serial download, serial debug, and nonintrusive single pin emulation ...

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... Figure 19. ULOAD mode can be used to upgrade your code in the field via any user defined download protocol. Configuring the SPI port on the ADuC836 as a slave possible to completely reprogram the 56 Kbytes of Flash/EE program memory in only 5 seconds (see Application Note uC007). ...

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... ADuC836 Using the Flash/EE Data Memory The 4 Kbytes of Flash/EE data memory are configured as 1024 pages, each of four bytes. As with the other ADuC836 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data regis- ters (EDATA1–A4) is used to hold the four bytes of data at each page ...

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... Flash/EE array.This command coded in 8051 assembly would appear as: MOV ECON,#06H ; Erase all Command ; 2 ms Duration Flash/EE Memory Timing Typical program and erase times for the ADuC836 are as follows: Normal Mode (operating on Flash/EE data memory) READPAGE (4 bytes) WRITEPAGE (4 bytes) VERIFYPAGE (4 bytes) ...

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... ADuC836 DAC The ADuC836 incorporates a 12-bit voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 k/100 pF. It has two selectable ranges nal band gap 2.5 V reference) and 12-bit or 8-bit mode.The DAC has a control register, DACCON, and two data registers, DACH/L ...

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... The endpoint nonlinearities conceptually illustrated in Figure 22 get worse as a function of output loading. Most of the ADuC836 data sheet specifications assume a 10 k resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 22 become larger ...

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... ADuC836 PULSEWIDTH MODULATOR (PWM) The PWM on the ADuC836 is a highly flexible PWM offering programmable resolution and input clock, and can be configured for any one of six different modes of operation.Two of these modes allow the PWM to be configured as a - DAC with bits of resolution ...

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... PWM1H/L, PWM1 (P1.1) goes low and remains low until the P1.0 PWM counter rolls over. In this mode, both PWM outputs are synchronized (i.e., once the PWM counter rolls over to 0, both PWM0 (P1.0) and PWM1 (P1.1) will go high). Figure 29. PWM Mode 3 –37– ADuC836 PWM1L PWM COUNTER PWM0H PWM0L PWM1H 0 P1.0 P1 ...

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... ADuC836 Mode 4: Dual NRZ 16-Bit - DAC Mode 4 provides a high speed PWM output similar to that of a - DAC. Typically, this mode will be used with the PWM clock equal to 12.58 MHz. In this mode, P1.0 and P1.1 are updated every PWM clock ( the case of 12.58 MHz). Over any 65536 cycles (16-bit PWM), PWM0 (P1.0) is high for PWM0H/L cycles and low for (65536 – ...

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... In this mode, the PLL output can be 12.58 MHz ± 20%. After the ADuC836 wakes up from power-down, user code may poll this bit to wait for the PLL to lock. If LOCK = 0, then the PLL is not locked. ...

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... MIN, and HOURS SFRs. To ensure that these registers are cleared, TCEN must be held low for at least 30.5 s (32 kHz). The time registers (HTHSEC, SEC, MIN, and HOUR) can be written only while TCEN is low. If the ADuC836 is in Power-Down mode, again with TIC inter- rupt enabled, the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053H ...

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... This register is incremented in 1-hour intervals once TCEN in TIMECON is active.The HOUR SFR counts from before rolling over to 0. SFR Address A5H Power-On Default Value 00H Reset Default Value 00H if TCEN = 0, previous value before reset if TCEN = 1 Bit Addressable No Valid Value decimal REV. A –41– ADuC836 ...

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... ADuC836 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC836 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR ...

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... POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies ( the ADuC836. It will DD DD indicate when any of the supply pins drops below one of four user-selectable voltage trip points from 2. 4.63 V. For cor- rect operation of the Power Supply Monitor function equal to or greater than 2 ...

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... The data is transferred as byte- wide (8-bit) serial data, MSB first. SS (Slave Select Input Pin), Pin 13 The Slave Select (SS) input pin is only used when the ADuC836 is configured in SPI Slave mode. This line is active low. Data is only received or transmitted in Slave mode when the SS pin is low, allowing the ADuC836 to be used in single master, multislave SPI configurations ...

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... SPIDAT Register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in Master mode. If the ADuC836 needs to assert the SS pin on an external slave device, a port digital output pin should be used. ...

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... ADuC836 SERIAL INTERFACE The ADuC836 supports a fully licensed interface is implemented as a full hardware slave and soft- ware master. SDATA (Pin 27) is the data I/O pin and SCLOCK (Pin 26) is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface ...

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... Bit EA in the IE SFR, i.e., ; Enabling I2C Interrupts for the ADuC836 MOV IEIP2,#01h ; enable I2C interrupt SETB EA On the ADuC836, an auto clear of the I2CI bit is implemented so this bit is cleared automatically on a read or write access to the I2CDAT SFR. 2 ...

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... ADuC836 DUAL DATA POINTER The ADuC836 incorporates both main and shadow data pointers. The shadow data pointer is selected via the data pointer control SFR (DPCON). DPCON also includes features such as automatic hardware post-increment and post-decrement, as well as automatic data pointer toggle. DPCON is described in Table XXIII. ...

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... SFR bit definitions. Parallel I/O The ADuC836 uses four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device ...

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... ADuC836 P1.2 to P1.7 The remaining Port 1 pins (P1.2 to P1.7) can only be configured as analog input (ADC) or digital input pins. By (power-on) default, these pins are configured as analog inputs, i.e., 1 written in the corresponding Port 1 register bit. To configure any of these pins as digital inputs, the user should write these port bits to configure the corresponding pin as a high impedance digital input ...

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... Q3 voltage of the transistor and interpret Logic 0. Reading the latch rather than the pin will return the correct value of 1. –51– ADuC836 DV DD HARDWARE SPI MISO (MASTER/SLAVE) ...

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... ADuC836 TIMERS/COUNTERS The ADuC836 has three 16-bit Timer/Counters:Timer 0,Timer 1, and Timer 2. The Timer/Counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each Timer/Counter consists of two 8-bit registers: THx and TLx ( and 2). All three can be configured to operate either as timers or event counters ...

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... TH0 and TL0 Timer 0 high byte and low byte. SFR Address = 8CH, 8AH, respectively. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8DH, 8BH, respectively. REV. A Table XXVII. TCON SFR Bit Designations –53– ADuC836 ...

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... ADuC836 TIMER/COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for Timer/ Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for both Timer 0 and 1. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler ...

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... CONTROL TR2 RELOAD RCAP2L RCAP2H CONTROL EXEN2 Figure 52.Timer/Counter 2, 16-Bit Autoreload Mode TL2 TH2 (8 BITS) (8 BITS CONTROL TR2 CAPTURE RCAP2L RCAP2H CONTROL EXEN2 Figure 53.Timer/Counter 2, 16-Bit Capture Mode –55– ADuC836 TF2 TIMER INTERRUPT EXF2 TF2 TIMER INTERRUPT EXF2 ...

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... ADuC836 T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1. Cleared by user software. 6 EXF2 Timer 2 External Flag. ...

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... Mode 1: 8-bit UART, variable baud rate Mode 2: 9-bit UART, fixed baud rate (f Mode 3: 9-bit UART, variable baud rate CORE CLK ALE RxD (DATA OUT) TxD (SHIFT CLOCK) Figure 54. UART Serial PortTransmission, Mode 0 –57– ADuC836 /12) CORE /64 /32) CORE CORE MACHINE MACHINE MACHINE CYCLE 1 CYCLE 2 ...

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... Traditionally, the baud rates in Modes 1 and 3 are determined by the overflow rate in Timer 1 or Timer 2, or both (one for transmit and the other for receive). On the ADuC836, however, the baud rate can also be generated via a separate baud rate generator to achieve higher baud rates and allow all three to be used for other functions. – ...

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... CONTROL OVERFLOW TL2 TH2 (8 BITS) (8 BITS) TR2 RELOAD RCAP2L RCAP2H TIMER 2 EXF 2 INTERRUPT CONTROL EXEN2 Figure 56.Timer 2, UART Baud Rates –59– ADuC836 ( ) ( = × Timer Overflow Rate f = and Mode Baud Rate 3 ( × 32 65536 Core RCAP2H RCAP2L Actual ...

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... The high integer dividers in a UART block means that high speed baud rates are not always possible using some particular crystals, e.g., using a 12 MHz crystal, a baud rate of 115200 is not possible. To address this problem, the ADuC836 has added a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates. ...

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... INTERRUPT SYSTEM The ADuC836 provides a total of 11 interrupt sources with two priority levels. The control and configuration of the interrupt system are carried out through three interrupt-related SFRs: the IE (Interrupt Enable) Register, IP (Interrupt Priority Register), and IEIP2 (Secondary Interrupt Enable/Priority SFR) Registers. Their bit definitions are given in the Tables XXXV to XXXVII. ...

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... ADuC836 Interrupt Priority The Interrupt Enable registers are written by the user to enable individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each inter- rupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of differ- ent priority occur at the same time, the higher level interrupt will be serviced first ...

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... It emits the low byte of the data pointer (DPL address, which is latched by ALE prior to data being placed on the bus by the ADuC836 (write operation the external data memory (read operation). Port 2 (P2) provides the data pointer page byte (DPP latched by ALE, followed by the data pointer high byte (DPH) ...

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... Connect the ground terminal of each of these capacitors directly to and the underlying ground plane. Finally, it should also be noticed that, at all times, the analog and digital ground pins on the ADuC836 line. In this mode, DD should be referenced to the same system ground reference point. Power-On Reset (POR) Operation voltage level of ...

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... ADuC836 since a ground loop would result. In these cases, tie the ADuC836’s AGND and DGND pins all to the analog ground plane, as illustrated in Figure 64b. In systems with only one ground plane, ensure that the digital and analog com- ...

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... ADuC836’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than the ADuC836 input pins. A value of 100  or 200  is usually suf- ficient to prevent high speed signals from coupling capacitively into the ADuC836 and affecting the accuracy of ADC conversions. ...

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... Download mode. This is accom- plished via a 1 k pull-down resistor that can be jumpered onto the PSEN pin, as shown in Figure 66. To get the ADuC836 into Download mode, simply connect this jumper and power-cycle the device (or manually reset the device manual reset button is available), and it will be ready to receive a new program serially ...

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... ADuC836 Typical System Configuration A typical ADuC836 configuration is shown in Figure 66. It sum- marizes some of the hardware considerations discussed in the previous paragraphs. Figure 66 also includes connections for a typical analog mea- surement application of the ADuC836, namely an interface to an RTD (Resistive Temperature Device). The arrangement shown is commonly referred 4-wire RTD configuration ...

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... QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC836. The system consists of the following PC based (Windows ware and software development tools: Hardware: ADuC836 Evaluation Board and Serial Port Cable Code Development: 8051 Assembler ...

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... Port 0, ALE, PSEN outputs = 100 pF; C LOAD 4 ADuC836 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a stable 12.583 MHz internal clock for the system. The core can operate at this frequency binary submultiple called Core_Clk, selected via the PLLCON SFR. 5 This number is measured at the default Core_Clk operating frequency of 1 ...

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... Variable Core_Clk Min Max 2t – 40 CORE t – 40 CORE t – 30 CORE 4t – 100 CORE t – 30 CORE 3t – 45 CORE 3t – 105 CORE 0 t – 25 CORE 5t – 105 CORE LLIV t PLIV t PXIZ t PXIX INSTRUCTION (IN) t PHAX ADuC836 Unit ...

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... ADuC836 Parameter EXTERNAL DATA MEMORY READ CYCLE t RD Pulsewidth RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX t RD Low to Valid Data In RLDV t Data and Address Hold after RD RHDX t Data Float after RD RHDZ t ALE Low to Valid Data In ...

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... LLWL WLWH t AVWL t QVWX t LLAX t t AVLL QVWH A0–A7 DATA A16–A23 A8–A15 Figure 73. External Data Memory Write Cycle –73– ADuC836 Variable Core_Clk Min Max Unit 6t – 100 ns CORE t – CORE t – CORE 3t – ...

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... ADuC836 Parameter UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold after Clock XHQX ALE (O) TxD (OUTPUT CLOCK) RxD (OUTPUT DATA) ...

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... MISO MSB IN t DSU REV. A Min 100 100 DAV MSB BITS 6–1 BITS 6–1 t DHD Figure 75. SPI Master ModeTiming (CPHA = 1) –75– ADuC836 Typ Max Unit 630 ns 630 ...

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... ADuC836 Parameter SPI MASTER MODE TIMING (CPHA = 0) t SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge DAV t Data Output Setup before SCLOCK Edge DOSU t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge ...

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... DAV DF DR BITS 6 MSB BITS 6 MSB DSU DHD Figure 77. SPI Slave ModeTiming (CPHA = 1) –77– Typ Max 330 330 SFS – LSB 1 LSB IN – ADuC836 Unit ...

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... ADuC836 Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SS t SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge ...

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... SUP MSB LSB t DSU t DHD SHD 1 2 Figure 79 Compatible InterfaceTiming –79– Max 0.9 300 300 ACK MSB t DSU F t DHD t RSU SUP S( REPEATED START ADuC836 Unit µs µs µs ns µs µs µs µ ...

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... ADuC836 1.03 0.88 0.73 SEATING PLANE VIEW A 0.23 0.11 BSC SQ PIN 1 INDICATOR 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE Revision History Location 4/03—Data Sheet changed from REV REV. A. Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 OUTLINE DIMENSIONS 52-Lead Metric Quad Flat Package [MQFP] (S-52) Dimensions shown in millimeters 14.15 13.90 SQ 2.45 13.65 MAX 39 40 7.80 TOP VIEW REF ...