ADUC836 Analog Devices, ADUC836 Datasheet - Page 29

• Manufacturer Part Number: ADUC836
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + Dual 16-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC836

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

NONVOLATILE FLASH/EE MEMORY
Flash/EE Memory Overview
The ADuC836 incorporates Flash/EE memory technology
on-chip to provide the user with nonvolatile, in-circuit, repro-
grammable code and data memory space. Flash/EE memory is
a relatively recent type of nonvolatile memory technology and is
based on a single transistor cell architecture. This technology is
basically an outgrowth of EPROM technology and was devel-
oped through the late 1980s. Flash/EE memory takes the flexible
in-circuit reprogrammable features of EEPROM and combines
them with the space efficient/density features of EPROM (see
Figure 15).
Because Flash/EE technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM, can be im-
plemented to achieve the space efficiencies or memory densities
required by a given design.
Like EEPROM, flash memory can be programmed in-system
at a byte level, although it must first be erased; the erase being
performed in page blocks. Thus, flash memory is often and more
correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit programma-
bility, high density, and low cost. Incorporated into the ADuC836,
Flash/EE memory technology allows the user to update program
code space in-circuit, without the need to replace one-time pro-
grammable (OTP) devices at remote operating nodes.
Flash/EE Memory and the ADuC836
The ADuC836 provides two arrays of Flash/EE memory for user
applications. 62 Kbytes of Flash/EE program space are provided
on-chip to facilitate code execution without any external dis-
crete ROM device requirements. The program memory can be
programmed in-circuit, using the serial download mode provided,
using conventional third party memory programmers, or via any
user defined protocol in User Download (ULOAD) mode.
A 4 Kbyte Flash/EE data memory space is also provided on-chip.
This may be used as a general-purpose, nonvolatile scratch pad
area. User access to this area is via a group of seven SFRs. This
space can be programmed at a byte level, although it must first be
erased in 4-byte pages.
REV. A
SPACE EFFICIENT/
Figure 15. Flash/EE Memory Development
DENSITY
TECHNOLOGY
EPROM
FLASH/EE MEMORY
TECHNOLOGY
TECHNOLOGY
EEPROM
REPROGRAMMABLE
IN-CIRCUIT
–29–
ADuC836 Flash/EE Memory Reliability
The Flash/EE program and data memory arrays on the ADuC836
are fully qualified for two key Flash/EE memory characteristics:
Flash/EE Memory Cycling Endurance and Flash/EE Memory
Data Retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four independent,
sequential events, which are defined as:
In reliability qualification, every byte in both the program and
data Flash/EE memory is cycled from 00H to FFH until a first
fail is recorded, signifying the endurance limit of the on-chip
Flash/EE memory.
As indicated in the Specification tables, the ADuC836 Flash/EE
Memory Endurance qualification has been carried out in
accordance with JEDEC Specification A117 over the industrial
temperature range of –40°C, +25°C, +85°C, and +125°C. The
results allow the specification of a minimum endurance figure
over supply and temperature of 100,000 cycles, with an endur-
ance figure of 700,000 cycles being typical of operation at 25°C.
Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. Again, the ADuC836 has been
qualified in accordance with the formal JEDEC Retention Life-
time Specification (A117) at a specific junction temperature
(T
memory is cycled to its specified endurance limit described above,
before data retention is characterized.This means that the Flash/EE
memory is guaranteed to retain its data for its full specified reten-
tion lifetime every time the Flash/EE memory is reprogrammed.
It should also be noted that retention lifetime, based on an activa-
tion energy of 0.6 eV, will derate with T
a. Initial page erase sequence
b. Read/verify sequence
c. Byte program sequence
d. Second read/verify sequence
J
= 55°C). As part of this qualification procedure, the Flash/EE
300
250
200
150
100
Figure 16. Flash/EE Memory Data Retention
50
0
40
50
T
J
60
JUNCTION TEMPERATURE – C
ADI SPECIFICATION
100 YEARS MIN.
70
AT T
J
= 55C
80
J
A Single Flash/EE
Memory Endurance
Cycle
, as shown in Figure 16.
90
ADuC836
100
110