ADUC836 Analog Devices, ADUC836 Datasheet - Page 42

• Manufacturer Part Number: ADUC836
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + Dual 16-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC836

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
or interrupt within a reasonable amount of time if the ADuC836
enters an erroneous state, possibly due to a programming error,
electrical noise, or RFI. The watchdog function can be disabled
by clearing the WDE (Watchdog Enable) bit in the Watchdog
Control (WDCON) SFR.When enabled, the watchdog circuit will
generate a system reset or interrupt (WDS) if the user program
fails to set the watchdog (WDE) bit within a predetermined
WDCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
ADuC836
Name
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
Description
Watchdog Timer Prescale Bits.
The Watchdog timeout period is given by the equation t
(0  PRE  7; f
Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog will generate an interrupt
response instead of a system reset when the watchdog timeout period has expired. This interrupt is not disabled by
the CLR EA instruction, and it is also a fixed, high priority interrupt. If the watchdog is not being used to monitor
the system, it can alternatively be used as a timer. The prescaler is used to set the timeout period in which an
interrupt will be generated. (See also Note 1, Table XXXIX in the Interrupt System section.)
Watchdog Status Bit.
Set by the watchdog controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.
Watchdog Enable Bit.
Set by user to enable the watchdog and clear its counters. If a 1 is not written to this bit within the watchdog timeout
period, the watchdog will generate a reset or interrupt, depending on WDIR.
Cleared under the following conditions: User writes 0, watchdog reset (WDIR = 0); hardware reset; PSM interrupt.
Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the
very next instruction must be a write instruction to the WDCON SFR. For example:
PRE3 PRE2
0
0
0
0
0
0
0
0
1
PRE3–0 > 1001
Watchdog Timer Control Register
C0H
10H
Yes
0
0
0
0
1
1
1
1
0
CLR
SETB
MOV
SETB
PLL
PRE1
0
0
1
1
0
0
1
1
0
EA
WDWR
WDCON, #72h
EA
= 32.768 kHz)
Table XIX. WDCON SFR Bit Designations
PRE0
0
1
0
1
0
1
0
1
0
Timeout
Period (ms)
15.6
31.2
62.5
125
250
500
1000
2000
0.0
; disable interrupts while writing
; to WDT
; allow write to WDCON
; enable WDT for 2.0s timeout
; enable interrupts again (if rqd)
–42–
amount of time (see PRE3–0 bits in WDCON). The watchdog
timer itself is a 16-bit counter that is clocked at 32.768 kHz.The
watchdog timeout interval can be adjusted via the PRE3–0 bits in
WDCON. Full control and status of the watchdog timer function
can be controlled via the Watchdog Timer Control SFR (WDCON).
The WDCON SFR can only be written by user software if the
double write sequence described in WDWR below is initiated on
every write access to the WDCON SFR.
Action
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Immediate Reset
Reserved
WD
= (2
PRE
 (2
9
/f
PLL
))
REV. A