ST10R172LT6 STMicroelectronics, ST10R172LT6 Datasheet - Page 21
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ST10R172LT6
Manufacturer Part Number
ST10R172LT6
Description
IC MCU 16BIT LV ROMLESS 100-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10R172LT6.pdf
(68 pages)
Specifications of ST10R172LT6
Core Processor
ST10
Core Size
16-Bit
Speed
50MHz
Connectivity
EBI/EMI, SSP, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
77
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Processor Series
ST10R1x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SSP, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
77
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2044
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10R172LT6
Manufacturer:
MPS
Quantity:
1 000
Company:
Part Number:
ST10R172LT6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST10R172LT6VJ029CNX
Manufacturer:
CYPRESS
Quantity:
10
9.2
The GPT2 module provides precise event control and time measurement. It includes two
timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an
input clock derived from the CPU clock via a programmable prescaler or with external signals.
The count direction (up/down) for each timer is programmable by software or altered
dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is
supported by the output toggle latch (T6OTL) of timer T6, which changes its state on each
timer overflow/underflow.
The state of T6OTL may be used to clock timer T5, or may be output on a port pin T6OUT. The
overflows/underflows of timer T6 reload the CAPREL register. The CAPREL register captures
the contents of T5 based on an external signal transition on the corresponding port pin
(CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows
absolute time differences to be measured or pulse multiplication to be performedwithout
software overhead.
F
Prescaler
Factor
Input
Frequency
Resolution
Period
CPU
=50MHz
GPT2
Table 6 GPT2 timer input frequencies, resolution and periods
Timer input selection
000b
4
12.5 MHz 6.25 MHz 3.125
80ns
5.24ms
001b
8
160ns
10.49ms
010b
16
MHz
320ns
20.97ms 41.94ms
011b
32
1.563
MHz
640ns
ST10R172L - GENERAL PURPOSE TIMERS
100b
64
781
KHz
1.28 us
83.88ms
101b
128
391
KHz
167.7ms
2.56 us
110b
256
195
KHz
5.12 us
335.5ms 671ms
111b
512
97.6
KHz
10.24 us
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