ST10R172LT6 STMicroelectronics, ST10R172LT6 Datasheet - Page 43

IC MCU 16BIT LV ROMLESS 100-TQFP

ST10R172LT6

Manufacturer Part Number
ST10R172LT6
Description
IC MCU 16BIT LV ROMLESS 100-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10R172LT6

Core Processor
ST10
Core Size
16-Bit
Speed
50MHz
Connectivity
EBI/EMI, SSP, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
77
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Processor Series
ST10R1x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SSP, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
77
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2044

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15.3.3 Multiplexed Bus
V
ALE cycle time = 6 TCL + 2
Parameter
ALE high time
Address (P1, P4), BHE
setup to ALE
Address (P0) setup to ALE
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
(with RW-delay)
Address float after RD,
(no RW-delay)
RD, WR low time
(with RW-delay)
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
Address to valid data in
(no RW-delay)
(with RW-delay)
(no RW-delay)
DD
= 3.3 V
1
0.3 V
1)
V
SS
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A
5
6
6m
7
8
9
10
11
12
13
14
15
16
17
+
= 0 V
t
C
CC 7 +
CC 3 +
CC 5 +
CC 5 +
CC 5 +
CC -5 +
CC –
CC –
CC 13 +
CC 23 +
SR –
SR –
SR –
SR –
+
Table 14 Multiplexed bus
t
F
(60 ns at 50-MHz CPU clock without waitstates)
Max. CPU Clock
= 50 MHz
min.
t
t
t
t
t
A
A
A
A
A
t
t
t
A
C
C
ST10R172L - ELECTRICAL CHARACTERISTICS
T
max.
5
15
5 +
15 +
15
+
20
+ 2
A
1
t
= -40°C to +85 °C
1
A
t
t
A
C
+
t
C
+
t
C
t
C
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
TCL - 3 +
TCL - 7 +
TCL - 5 +
TCL - 5 +
TCL - 5 +
-5 +
2TCL - 7+
3TCL - 7 +
t
A
t
t
t
t
t
A
A
A
A
A
t
C
t
C
C
L
= 50 pF
max.
5
TCL + 5
2TCL - 15
+
3TCL - 15
+
3TCL - 15
+
4TCL - 20
+ 2
1
t
t
t
C
C
A
t
A
+
+
t
C
t
1
C
43/68
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1

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