C8051F988-GM Silicon Laboratories Inc, C8051F988-GM Datasheet - Page 18

• Manufacturer Part Number: C8051F988-GM
• Description: IC MCU 8BIT 4KB FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F988-GM

• Program Memory Type: FLASH
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 24-UQFN Exposed Pad, 24-HUQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, Enhanced UART, Enhanced SPI
• Maximum Clock Frequency: 7 KHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F996DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1959-5

C8051F99x-C8051F98x
18
C2CK/RST
C2CK/RST
GND
GND
GND
GND
VDD
VDD
Programming
Programming
Reset/PMU
C2D
Reset/PMU
C2D
Power On
Power On
Hardware
Hardware
Debug /
Debug /
XTAL1
XTAL2
XTAL3
XTAL4
XTAL1
XTAL2
XTAL3
XTAL4
Wake
Reset
Wake
Reset
VREG
VREG
SmaRTClock
SmaRTClock
Low Power
Low Power
24.5 MHz
24.5 MHz
Precision
Oscillator
Oscillator
Oscillator
Oscillator
Precision
Oscillator
Oscillator
Oscillator
Oscillator
External
External
20 MHz
20 MHz
Power
Controller Core
Digital
Power
System Clock
Controller Core
Digital
System Clock
Circuit
Configuration
Circuit
Configuration
Program Memory
Program Memory
Figure 1.1. C8051F980 Block Diagram
Figure 1.2. C8051F981 Block Diagram
CIP-51 8051
256 Byte SRAM
256 Byte XRAM
CIP-51 8051
256 Byte SRAM
256 Byte XRAM
8 kB ISP Flash
8 kB ISP Flash
SYSCLK
SYSCLK
Engine
Engine
CRC
CRC
SFR
SFR
Bus
Bus
Rev. 1.0
Internal
12-bit
ADC
VREF
Timers 0,
Timers 0,
SMBus
SMBus
6-bit
IREF
1, 2, 3
Analog Peripherals
6-bit
IREF
UART
1, 2, 3
Analog Peripherals
UART
Digital Peripherals
PCA/
WDT
Digital Peripherals
PCA/
WDT
Port I/O Configuration
SPI
Port I/O Configuration
SPI
Crossbar Control
Crossbar Control
CP0
CP0
External
VREF
Comparator
Comparator
A
M
U
X
+
+
Crossbar
-
Crossbar
-
Decoder
Decoder
Priority
Priority
IREF0
IREF0
Sensor
VREF
Temp
VDD
GND
Drivers
Drivers
Drivers
Drivers
Drivers
Drivers
Port 0
Port 1
Port 0
Port 1
Port 2
Port 2
P1.0
P1.1
P1.0
P1.1
P0.2/XTAL1
P0.3/XTAL2
P0.2/XTAL1
P0.3/XTAL2
P0.0
P0.1
P0.4/TX
P0.5/RX
P0.6
P0.7/IREF0
P1.0/CP0+
P1.1/CP0-
P1.2
P1.3
P1.5
P1.6/XTAL3
P1.7/XTAL4
P0.0/VREF
P0.1/AGND
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
P1.0/CP0+
P1.1/CP0-
P1.2
P1.3
P1.5
P1.6/XTAL3
P1.7/XTAL4
P2.7/C2D
P2.7/C2D