C8051F988-GM Silicon Laboratories Inc, C8051F988-GM Datasheet - Page 93

• Manufacturer Part Number: C8051F988-GM
• Description: IC MCU 8BIT 4KB FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F988-GM

• Program Memory Type: FLASH
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 24-UQFN Exposed Pad, 24-HUQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, Enhanced UART, Enhanced SPI
• Maximum Clock Frequency: 7 KHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F996DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1959-5

7.5.
The SFRs used to enable and configure the comparator are described in the following register
descriptions. The comparator must be enabled by setting the CP0EN bit to logic 1 before it can be used.
From an enabled state, a comparator can be disabled and placed in a low power state by clearing the
CP0EN bit to logic 0.
Important Note About Comparator Settings: False rising and falling edges can be detected by the
Comparator while powering on or if changes are made to the hysteresis or response time control bits.
Therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a
short time after the comparator is enabled or its mode bits have been changed. The Comparator Power Up
Time is specified in Section “Table 4.14. Comparator Electrical Characteristics” on page 61.
(Programmed with CP0HYP Bits)
Comparator Register Descriptions
Positive Hysteresis Voltage
INPUTS
OUTPUT
VIN+
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis
CP0-
VIN+
CP0+
VIN-
Disabled
V
OL
V
OH
+
_
Figure 7.2. Comparator Hysteresis Plot
CP0
Positive Hysteresis
Maximum
OUT
Rev. 1.0
Negative Hysteresis
Disabled
C8051F99x-C8051F98x
Negative Hysteresis
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis Voltage
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