MC908JB16DWE Freescale Semiconductor, MC908JB16DWE Datasheet - Page 23

• Manufacturer Part Number: MC908JB16DWE
• Description: IC MCU 16K FLASH 6MHZ USB 28SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB16DWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SCI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C/SCI/SPI/USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MC68HC908JB16
Freescale Semiconductor
—
Rev. 1.1
Figure
10-10 TIM Channel 1 Status and Control Register (TSC1) . . . . . . . 156
10-11 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
10-12 TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . . 160
10-13 TIM Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . . . . . . 160
10-14 TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . . 160
10-15 TIM Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . . . . . . 160
11-1 USB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 164
11-2 USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
11-3 Supported Transaction Types Per Endpoint. . . . . . . . . . . . . . 169
11-4 Supported USB Packet Types . . . . . . . . . . . . . . . . . . . . . . . . 170
11-5 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11-6 SOP, Sync Signaling, and Voltage Levels . . . . . . . . . . . . . . . 171
11-7 EOP Transaction Voltage Levels . . . . . . . . . . . . . . . . . . . . . . 173
11-8 EOP Width Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
11-9 External Low-Speed Device Configuration . . . . . . . . . . . . . . . 176
11-10 Regulator Electrical Connections . . . . . . . . . . . . . . . . . . . . . . 177
11-11 Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11-12 Differential Input Sensitivity Range. . . . . . . . . . . . . . . . . . . . . 179
11-13 Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11-14 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . .180
11-15 USB Address Register (UADDR) . . . . . . . . . . . . . . . . . . . . . . 182
11-16 USB Interrupt Register 0 (UIR0) . . . . . . . . . . . . . . . . . . . . . . . 183
11-17 USB Interrupt Register 1 (UIR1) . . . . . . . . . . . . . . . . . . . . . . . 185
11-18 USB Interrupt Register 2 (UIR2) . . . . . . . . . . . . . . . . . . . . . . . 188
11-19 USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . . . . 189
11-20 USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . . . . 190
11-21 USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . . . . 191
11-22 USB Control Register 3 (UCR3) . . . . . . . . . . . . . . . . . . . . . . . 193
11-23 USB Control Register 4 (UCR4) . . . . . . . . . . . . . . . . . . . . . . . 195
11-24 USB Status Register 0 (USR0). . . . . . . . . . . . . . . . . . . . . . . . 196
11-25 USB Status Register 2 (USR1). . . . . . . . . . . . . . . . . . . . . . . . 197
11-26 USB Endpoint 0 Data Registers (UE0D0–UE0D7). . . . . . . . . 198
11-27 USB Endpoint 1 Data Registers (UE1D0–UE1D7). . . . . . . . . 199
11-28 USB Endpoint 2 Data Registers (UE2D0–UE2D7). . . . . . . . . 200
11-29 OUT Token Data Flow for Receive Endpoint 0. . . . . . . . . . . . 202
List of Figures
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Technical Data
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