MC908JB16DWE Freescale Semiconductor, MC908JB16DWE Datasheet - Page 72

• Manufacturer Part Number: MC908JB16DWE
• Description: IC MCU 16K FLASH 6MHZ USB 28SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB16DWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SCI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C/SCI/SPI/USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Configuration Register (CONFIG)
5.4 Configuration Register
Technical Data
72
NOTE:
* LVIDR, LVI5OR3, URSTD, and LVID bits are reset by POR (power-on reset) or LVI reset only.
Address:
Reset:
LVIDR — LVI Disable Bit for V
There is no LVI circuit for V
LVI5OR3 — LVI Trip Point Voltage Select Bit for V
URSTD — USB Reset Disable Bit
LVID — LVI Disable Bit for V
Read:
Write:
LVIDR disables the LVI circuit for V
Voltage Inhibit
LVI5OR3 selects the trip point voltage of the LVI circuit for V
(See
URSTD disables the USB reset signal generating an internal reset to
the CPU and internal registers. Instead, it will generate an interrupt
request to the CPU. (See
(USB).)
LVID disables the LVI circuit for V
Inhibit
1 = LVI circuit for V
0 = LVI circuit for V
1 = LVI trips at 3.3V
0 = LVI trips at 2.4V
1 = USB reset generates a USB interrupt request to CPU
0 = USB reset generates a chip reset
1 = LVI circuit for V
0 = LVI circuit for V
$001F
LVIDR
Bit 7
Section 18. Low-Voltage Inhibit
0*
Configuration Register (CONFIG)
(LVI).)
Figure 5-1. Configuration Register (CONFIG)
LVI5OR3
0*
6
(LVI).)
URSTD
REG
REG
DD
DD
0*
5
REGA
disabled
enabled
Section 11. Universal Serial Bus Module
DD
disabled
enabled
REG
LVID
.
0*
4
DD
REG
. (See
SSREC
3
0
. (See
(LVI).)
Section 18. Low-Voltage
MC68HC908JB16
COPRS
Section 18. Low-
Freescale Semiconductor
2
0
DD
STOP
1
0
—
DD
Rev. 1.1
COPD
.
Bit 0
0