MC908JB16DWE Freescale Semiconductor, MC908JB16DWE Datasheet - Page 232

• Manufacturer Part Number: MC908JB16DWE
• Description: IC MCU 16K FLASH 6MHZ USB 28SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB16DWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SCI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C/SCI/SPI/USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Communications Interface
12.9.2 SCI Control Register 2
Technical Data
232
NOTE:
PTY — Parity Bit
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
SCI control register 2:
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. (See
bit.
•
M
0
1
0
0
1
1
Serial Communications Interface Module (SCI)
Control Bits
1 = Odd parity
0 = Even parity
Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
– Enables the TC bit to generate transmitter CPU interrupt
– Enables the SCRF bit to generate receiver CPU interrupt
– Enables the IDLE bit to generate receiver CPU interrupt
requests
requests
requests
requests
PEN and
PTY
0X
0X
10
11
10
11
Table 12-5. Character Format Selection
Start
Bits
1
1
1
1
1
1
Data
Bits
8
9
7
7
8
8
Table
Character Format
Parity
None
None
Even
Even
Odd
Odd
12-5.) Reset clears the PTY
MC68HC908JB16
Freescale Semiconductor
Stop
Bits
1
1
1
1
1
1
Character
Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
—
Rev. 1.1